Creonic to Provide Three LDPC Decoder IP Cores for DOCSIS 3.1

Kaiserslautern, Germany, Oct 28, 2015 - Creonic GmbH, a leading IP core supplier for communications, revealed today the availability of three new IP cores for the new DOCSIS 3.1 standard. DOCSIS 3.1 technology consists of the newest and first-rate of digital communication technologies such as LDPC encoding with very high modulation orders (up to 4096-QAM) and more than 1GHz of usable spectrum. It therefore supports speeds of up to 10 Gbps in downstream and 1 Gbps in upstream.

Creonic offers three LDPC decoder IP cores for the downstream of DOCSIS 3.1. The first decoder takes care for the physical link layer channel (PLC). It comprises 16-QAM demapper, derandomizer, deinterleaver and LDPC decoder. The second decoder performs decoding of the next codeword pointer (NCP) and comprises QPSK/16-QAM/64-QAM demapper, derandomizer and LDPC decoder. The third decoder is responsible for the data path and comprises LDPC and BCH decoder including support for shortening. It offers throughputs beyond 2.3 Gbps on state-of-the-art FPGAs and provides an outstanding area efficiency.

The IP cores are available for FPGA and ASIC platforms either as un-encrypted or encrypted source code. They come with HDL simulation models, VHDL testbench and comprehensive documentation. Furthermore, bit-accurate software models for usage in customer's own C/C++/Matlab simulation environments are available.

About Creonic

Creonic is an ISO 9001:2008 certified provider of ready-for-use IP cores for many algorithms of communications such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. The product portfolio covers standards like DVB-S2X, LTE, DVB-RCS2, DOCSIS 3.1, WiFi, WiGig, and UWB. The products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance. For more information please visit www.creonic.com.

Contact:

Senay Unal

Manager, Marketing and Sales

Email Contact

+49 631 3435 9886



Read the complete story ...


Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

True Circuits:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Reverie: All That Glitters is not Past
More Editorial  
Jobs
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Technical Marketing Manager Valley for EDA Careers at San Jose, CA
Digital and FPGA Hardware Designer for Giga-tronics Incorporated at San Ramon, CA
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
SoC Design Engineer for Intel at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Upcoming Events
European 3D Summit 2017 at 3, parvis Louis Néel 38054 Grenoble France - Jan 23 - 25, 2017
3D Printing Electronics Conference at High Tech Campus 1, 5656 Eindhoven Eindhoven Netherlands - Jan 24, 2017
DesignCon 2017 at Santa Clara Convention Center Santa Clara CA - Jan 31 - 2, 2017
Embedded Neural Network Summit at San Jose CA - Feb 1, 2017
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy