Verific Design Automation's Parser Platform Integrated with Tortuga Logic's Hardware Security Design and Analysis Toolkit

Thoroughly Tested Parsers Let Tortuga Logic Focus on Software to Identify Security Vulnerabilities in Hardware Designs

ALAMEDA, CALIF. — October 20, 2015 —  Tortuga Logic, transforming the way hardware designers and system architects test the security of hardware design, has licensed the Parser Platform from Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF parsers used throughout the semiconductor industry.

Verific's SystemVerilog and VHDL parsers have been implemented as the front end to Prospect, Tortuga Logic's Hardware Security Design and Analysis Toolkit that uncovers hidden bugs and proves the absence of vulnerabilities in hardware designs.

"Verific's Parser Platform is an important component of our hardware security software," confirms Dr. Jason Oberg, co-founder and chief executive officer (CEO) of Tortuga Logic. "We were able to save countless hours by partnering with Verific. We used its thoroughly tested parsers and were able to focus on developing software that identifies security vulnerabilities in hardware designs."

Leveraging Verific's Parser Platform, Prospect reads a register transfer level (RTL) description of the design and performs a thorough analysis to uncover a broad range of vulnerabilities. It does so by automatically generating SystemVerilog assertions and instrumentation from a high-level description of the security properties.

"Security is becoming an increasing concern and we applaud Tortuga Logic's security experts for tackling this problem," says Michiel Ligthart, Verific's president and chief operating officer. "The founders' decision to choose our parser platform enabled the early release of this significant new toolset and keep system designs secure."

Verific's Parser Platforms are in production and development use today at companies worldwide, from cybersecurity startups such as Tortuga Logic to established Fortune 500 semiconductor vendors. Applications vary from analysis, simulation, formal verification and synthesis to emulation and virtual prototyping, in-circuit debug and design-for-test. Parser Platforms are distributed as C++ source code and compile on all 32- and 64-bit Unix, Linux and Windows operating systems. Its Parser Platforms include support for SystemVerilog, Verilog, VHDL and UPF, and provide C++, Python and Perl APIs.

About Tortuga Logic

Tortuga Logic, Inc., part of the emerging Design-for-Security market, has the goal to solve security-specific problems, minimizing security breaches in hardware and systems by automating the process of verifying their security properties. It has developed a comprehensive Hardware Security Design and Analysis Toolkit, transforming the way hardware designers and system architects test the security of hardware designs. More information can be found at:  www.tortugalogic.com Email: Email Contact

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email:  Email Contact. Website:  www.verific.com.




Review Article Be the first to review this article
CST: Webinar October 19, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Field Application Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
Preparing for the Cognitive Era: Education, Occupation and You at SJSU Student Union Theater 211 South 9th Street San Jose CA - Oct 18, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise