Real Intent to Exhibit at Design Solution Forum 2015 in Japan

SUNNYVALE, Calif. and YOKOHAMA, Japan – Sept. 24, 2015 –


Real Intent, a leading provider of SoC and FPGA sign-off verification solutions


Will exhibit its Ascent™ and Meridian™ products for accelerating advanced sign-off, at the Design Solution Forum 2015 in Yokohama, Japan next week. Sponsored by the Japan Electronics Show Association, this seminar brings together design engineers from throughout Japan to share the latest information about design, verification, software and FPGA technology trends. Organizers anticipate this event will to lead to improved and optimized engineering, the creation of new business, individual reskilling, career improvement, and valuable exchange of ideas and technical information including design case studies and technological trends.

Yasuo Torisawa, Country Manager at Real Intent KK, will help attendees learn more about Real Intent’s advanced solutions. Its Ascent products improve QoR and productivity of design teams by finding elusive bugs and getting rid of sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation. Its Meridian products accelerate sign-off verification of clock domain crossings and SDC in 500+M gate SoC designs.


Friday, Oct. 2, 2015 (11:30-15:30)
Shin-Yokohama Kokusai International Hotel

Manor House South Building, Exhibition in 2F

Kohoku-ku, Yokohama, 222-0033 Japan

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit for more information.

Real Intent and the Real Intent logo are registered trademarks, and Meridian, iDebug and Ascent are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.

CDC:      Clock Domain Crossing
EDA:      Electronic Design Automation
FPGA:    Field Programmable Gate Array
RTL:       Register Transfer Level
SDC       Synopsys Design Constraints
SoCs:     Systems-on-Chip
VHDL:   Very High-Level Design Language

Press contact:
Sarah Miller for Real Intent
ThinkBold Corporate Communications
Email Contact

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