UltraSoC adds deadlock detection to SoC analysis, debug and profiling tools

Addresses “one of the trickiest problems in SoC development”

CAMBRIDGE, United Kingdom – UltraSoC today announced that it has added deadlock detection capabilities within its products for SoC analysis, profiling and debug. The new features allow SoC architects, developers and debug engineers to detect and diagnose hard-to-find corner cases which can cause complex SoCs to hang or stall intermittently and unpredictably, sometimes after days of continuous normal operation.

“Our customers tell us that intermittent deadlock and stall conditions are amongst the hardest problems to solve in their SoC designs,” said Gadge Panesar, UltraSoC CTO. “These conditions are a major contributor to the current crisis in the SoC industry. Conventional approaches either ignore the problem, or attempt to deal with it by generating massive, unmanageable data sets. UltraSoC takes a smarter approach, focusing on generating meaningful, actionable information; for the first time chip design teams can truly understand the behavior of today’s complex SoCs.”

UltraSoC technology allows chip designers to efficiently and intelligently “look inside” their products, at wire speed, during normal operation. The new deadlock detection capabilities are targeted at particularly difficult conditions that can cause devices to fail intermittently and unpredictably, including bus and software deadlocks.

Bus deadlocks occur when a processor is waiting for a response from another sub-system via an on-chip bus such as AXI or OCP, but the response never arrives. Traditionally, the only way of isolating such problems has been to attempt to continuously trace and output all bus activity, requiring a high-bandwidth off-chip connection to gather the data, and difficult offline analysis software of huge data-sets. The UltraSoC solution uses a “smart” on-chip bus monitor that is protocol-aware and can be triggered when the time taken for a bus transaction exceeds a programmable limit. When triggered by a deadlocked transaction, the system identifies the complete transaction ID and address, guiding the engineer’s attention to both the master and slave of the problem.

Software deadlocks are increasingly common in today’s SoCs. In a typical scenario, two different software processes might use a locking mechanism to govern shared access to common on-chip resources: for example another core, hardware peripherals or the capabilities of another software process. Problems can arise when each CPU believes that the other has locked its access to the shared resources. In this case UltraSoC provides an on-chip status monitor which can be used to detect the fault condition, halt the processors and initiate data capture to isolate the problem. As multi-core systems and heterogenous architectures become more common this becomes ever more important. UltraSoc is a vendor-neutral architecture, supporting many different bus protocols and processor families (including ARM, MIPS, Xtensa, CEVA and others), making it possible to solve these situations.

SoC debug and silicon validation are key challenges facing the global electronics industry today. UltraSoC’s technology creates an on-chip debug infrastructure that enables pre- and post-silicon debug, de-risking the process of chip design, improving time-to-market, increasing quality and reducing costs.

UltraSoC will be demonstrating its new deadlock detection capabilities at  ARM TechCon(Booth 215, Santa Clara Convention Center, CA, 10 – 12 November 2015) and  Semisrael Expo (Booth 27, Avenue Convention Center, Airport City, Israel, 17 November 2015).




Review Article Be the first to review this article
Featured Video
Editorial
More Editorial  
Jobs
Staff Software Engineer - (170059) for brocade at San Jose, CA
Test Development Engineer(Job Number: 17001697) for Global Foundaries at Santa Clara, CA
Engr, Elec Des 2 for KLA-Tencor at Milpitas, CA
Technical Support Engineer Germany/UK for EDA Careers at San Jose, CA
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
ASIC Design Engineer for Ambarella at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy