SUNNYVALE, CALIF. – Sept. 10, 2015 –
Real Intent, a leading provider of SoC and FPGA sign-off verification solutions
Will exhibit its Ascent™ and Meridian™ products for SoC sign-off at the Synopsys® Designer Community Expo (DCE) at the Synopsys Users Group (SNUG®) Austin 2015 event next week in Austin, Texas. This event brings companies together from across the industry to showcase their latest solutions and their interoperability with Synopsys. As part of the IC Verification community at DCE, Real Intent will showcase its Meridian CDC and Ascent X-verification System (XV) software working with Synopsys’ industry-leading VCS® functional verification solution and Synopsys’ de facto standard Verdi® debug solution. Ascent products improve QoR and productivity of design teams by finding elusive bugs and getting rid of sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation. Meridian products accelerate sign-off verification of clock domain crossings and SDC in 500+M gate SoC designs.
The SNUG Designer Community Expo (DCE) is a unique networking event featuring Synopsys and its ecosystem partners from across the electronics industry. At SNUG DCE, Synopsys users can interact with exhibitors and see the latest design enablement solutions spanning six designer communities: Compute and Design Infrastructure, Custom Design and AMS Verification, IC Design, IC Verification, IP and Prototyping & FPGA Design. The IC Verification community focuses on functional verification and debug flows, including: simulation, static and formal verification, mixed-HDL, AMS verification, testbench technology, debug automation, verification IP, emulation and IC verification ecosystem partners. The Synopsys Users Group is open to all Synopsys customers. DCE is open to all registered attendees of SNUG Austin.
Friday, September 18, 2015, 5 - 7 p.m., SNUG Designer Community Expo
Hyatt Regency Austin
208 Barton Springs Rd., Austin, TX 78704
Phone: (512) 477-1234
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit http://www.realintent.com for more information.
Real Intent and the Real Intent logo are registered trademarks, and Meridian, iDebug and Ascent are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
CDC Clock Domain Crossing
FPGA Field Programmable Gate Array
HDL High-Level Design Language
IC Integrated Circuit
IP Intellectual Property
QoR Quality of Results
RTL Register Transfer Level
SDC Synopsys Design Constraints
SoC System on Chip
VHDL Very High-Level Design Language
Sarah Miller for Real Intent
ThinkBold Corporate Communications