Vtool Relies on Verific Design Automation’s Parser Platform to Drive Disruptive, Functional Verification Platform

Verific’s Parser Platform Ensures Integration with SystemVerilog and UVM

ALAMEDA, CALIF. –– July 14, 2015 –– Verific Design Automation, recognized as the leading supplier of hardware description language (HDL) parsers used throughout the semiconductor industry, today announced electronic design automation (EDA) newcomer Vtool has chosen Verific’s parsers for use with its functional verification platform.

Vtool intends to revolutionize integrated circuit (IC) design and verification with an efficient platform that includes all verification elements, from plan formulation through testbench implementation and debug. Verific’s SystemVerilog and VHDL parsers are in use as the front end to Vtool’s Environment Builder and VIP Builder, enabling Vtool to develop its functional verification platform faster and more cost effectively. 

Selecting Verific’s Parser Platform also ensured Vtool’s functional verification platform could be integrated with existing SystemVerilog-based universal verification methodology (UVM) and verification intellectual property (VIP) technologies.

“Verific’s reputation is well known throughout the semiconductor and EDA industry, and is well deserved,” remarks Hagai Arbel, Vtool’s chief executive officer. “Its parsers easily integrated with our functional verification platform, saving us time and resources that could be deployed elsewhere. If we had a question, we knew its customer support team was a phone call or email away and always responsive.”

Verific’s Parser Platforms are in production and development use today at companies worldwide, from EDA startups to established Fortune 500 semiconductor vendors. Applications vary from analysis, simulation, formal verification and synthesis to emulation and virtual prototyping, in-circuit debug and design-for-test. Parser Platforms are distributed as C++ source code and compile on all 32- and 64-bit Unix, Linux and Windows operating systems. Its Parser Platforms include support for SystemVerilog, Verilog, VHDL and UPF, and provide C++, Python and Perl APIs.

“Vtool has undertaken a huge but important challenge to revolutionize chip verification,” Michiel Ligthart, Verific’s president and chief operating officer, adds. “It gives us great pleasure to play a role in helping bring efficiency and precision to the verification bottleneck.”

About Vtool

Vtool of Tel Aviv, Israel, provides a disruptive functional verification platform that makes the painstaking functional verification process efficient and precise, thanks to user-friendly automation. Integrating smoothly with existing SystemVerilog UVM and Verification IP

technologies, Vtool’s all-in-one interface lets verification teams focus on the most essential parts, resulting in easier, faster time-to-tapeout.  For more information, visit: www.thevtool.com

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: Email Contact Website: www.verific.com

###

Verific Design Automation and Vtool acknowledge trademarks or registered trademarks of other organizations for their respective products and services.




Review Article Be the first to review this article
CST: Webinar September 14, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Real Intent: Leveraging on Investments
More Editorial  
Jobs
Field Application Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise