TSMC Certifies Cadence Innovus Implementation System on 16-nanometer FinFET Plus Process

TSMC and Cadence are actively collaborating to certify the Innovus Implementation System on the TSMC 10nm FinFET process

SAN JOSE, Calif., June 8, 2015 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Cadence® Innovus™ Implementation System has achieved v1.0 Design Rule Manual (DRM) certification from TSMC for its 16-nanometer FinFET Plus (16FF+) process. The Innovus Implementation System successfully passed rigorous testing and has been validated by TSMC on high-performance reference designs in order to provide customers with a fast path to design closure. Additionally, Cadence and TSMC are collaborating on the certification of the Innovus Implementation System on the 10-nanometer (nm) FinFET process. The certification for the latest version of 10nm DRM and SPICE models is currently on target for completion in June 2015.

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The Innovus Implementation System is a next-generation physical implementation tool that enables system-on-chip (SoC) developers to deliver high-quality designs with highly competitive power, performance and area (PPA), while accelerating time to market. The tool provides key technology for the 16FF+ process and supports floorplanning, placement and routing with integrated color-/pin-access-/variability-aware timing closure, clock tree and power optimization.

TSMC's certification of Innovus Implementation System capabilities include:

  • GigaPlace™ placement technology that improves electrical and physical design closure
  • Integration with Cadence Quantus™ QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, and Physical Verification System provides a fast path to design closure

For more information on the Innovus Implementation System, please visit www.cadence.com/news/innovus.  

"The Innovus Implementation System enables high quality results and fast path to design closure with its breakthrough placement and optimization capabilities and multithreading," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. "TSMC's certification of the Innovus Implementation System gives customers more confidence that their 16FF+ designs can meet aggressive PPA targets so they can deliver high-quality designs to market faster. We continue to closely partner with TSMC on the advancement of 16FF+ designs so our customers can stay at the forefront of silicon technology."

"The Cadence and TSMC R&D teams collaborated closely on the certification of the Innovus Implementation System, and we are committed to enabling our mutual customers to deliver innovative, advanced-node designs to market," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "With this certification, designers can achieve rapid design closure while reaping the benefits of higher performance and lower power consumption on TSMC's 16FF+ process."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and GigaPlace, Innovus, Quantus, Tempus and Voltus and are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

This press release contains certain forward-looking statements, including expectations for technology and product certification, availability, and performance that are based on our current expectations and involve numerous risks and uncertainties that may cause these forward-looking statements to be inaccurate. Risks that may cause these forward-looking statements to be inaccurate include among others: pending certification may not be achieved for unforeseen reasons, or the other risks detailed from time-to-time in our Securities and Exchange Commission filings and reports, including, but not limited to, our most recent quarterly report on Form 10-Q. We do not intend to update the information contained in this news release.

For more information, please contact:
Cadence Newsroom
Email Contact

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To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/tsmc-certifies-cadence-innovus-implementation-system-on-16-nanometer-finfet-plus-process-300095162.html

SOURCE Cadence Design Systems, Inc.

Cadence Design Systems, Inc.
Web: http://www.cadence.com

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