Mentor Graphics Enterprise Verification Platform Delivers New Levels of Performance and Low Power Verification Productivity

WILSONVILLE, Ore., June 5, 2015 — (PRNewswire) —


  • Questa® Simulation regression test speeds improved by up to 4X
  • Questa Simulation with Visualizer™ Debug Environment 2-5X faster and smaller
  • Questa Verification Management coverage data collection up to 10X faster
  • Questa Formal Apps increased performance by up to 8X
  • Questa Power Aware introduces leading support for UPF 2.1

Mentor Graphics Corporation (NASDAQ: MENT) today announced enhancements to the Mentor® Enterprise Verification Platform (EVP) that offer new levels of performance and productivity across the platform in simulation, debug, formal, coverage closure and low power verification. 

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The cornerstone of the Mentor EVP, the Questa Simulation engine, now runs up to 4X faster by improvements in both raw VHDL/Verilog performance and incremental flows, coupled with a new checkpoint/restore/modify/run flow which saves hours on each long simulation that can share a common "setup" time before unique stimulus is applied. The Questa Simulation engine has also been enhanced with new native Questa fast logging technology which enables debug mode simulations to run 2-4X faster and require up to 3X less memory. It deploys "smart" reconstruction techniques when coupled with the Visualizer Debug Environment, which also significantly reduces debug file sizes. The combination of Questa Simulation and Visualizer Debug provides users the fastest debug turnaround times available on the market today.

"After just a few months of use, Visualizer has led to dramatically improved verification performance," said Ramesh Shanmugam, Pixelworks senior manager of verification and methodology. "This is largely because the way it's used — for post-processing analysis of simulation data — is a much more efficient, higher-throughput means of debugging than using a simulator in interactive mode."

In coverage-driven verification flows, often the time it takes to merge coverage results from hundreds if not thousands of individual tests can be a major verification performance bottleneck. The Questa Verification Management now collects and analyzes coverage data up to 10X faster with enhanced merging and ranking technology. It quickly generates a unified coverage database (UCDB) that can be accessed by the Accellera UCIS standard interchange format, enabling users to quickly assess their current quality of verification and reduce their coverage closure time.

The Questa Formal engine, now up to 8X faster, speeds up verification with its increasing number of formal apps such as clock domain crossing (CDC), property checking, X-state analysis, connectivity checking, and security checking. The Questa Formal works seamlessly with and perfectly complements the Questa Simulation such that the performance improvements to both engines deliver faster overall time to results, and enables customers to pull in their verification schedules and improve end-product quality.

The Questa Power Aware Simulation, the fastest native UPF/RTL simulator, announces its first-to-market support of IEEE 1801 UPF 2.1. The Questa Power Aware includes automatic static and dynamic low power UPF checks that help user quickly verify that their UPF-derived power management structures and behaviors are correct, and automatic UPF-driven coverage and testplan generation that will help users understand and track exactly what is needed for complete low power coverage closure. The Questa Power Aware can also now generate functionally-equivalent UPF 1.0 from UPF 2.1 in order to support UPF-based flows with downstream tools that do not yet fully support UPF2.1 enabling users to take advantage of more productive low power verification methodologies.

For power-aware debug, the Visualizer Debug Environment provides a complete set of windows that enable users to see all UPF-generated structures; power domains, source/sync crossings, isolation, shifters, etc. plus any UPF violations and waveforms of corruptions in one tool. Its unified schematic views and highlights of UPF instrumentations directly in the RTL source help verification engineers easily understand and explore the power management structures within the context of the RTL design.

"Our customers demand high-performance verification engines that achieve the fastest results in all facets of the verification flow:  regression testing, debug and coverage," said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. "The Mentor Enterprise Verification platform delivers best-in-class performance, productivity and low power analysis in a single, integrated verification platform."

The latest simulation performance, productivity and low power verification gains are available in the Questa 10.4 release that is available immediately.

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.24 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site:

Mentor Graphics, Mentor and Questa are registered trademarks and Visualizer is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

For more information, please contact:
David Smith
Mentor Graphics
Email Contact

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Mentor Graphics Corporation

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