June 8-10, 2015, Moscone Convention Center, Booth #2014
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries.
At the Design Automation Conference (DAC), True Circuits will showcase its new Ultra PLL hard macros that are well suited for the most demanding chip applications, including high-speed SerDes and ADC input clocks. The state-of-the-art Ultra PLL is designed as an ultra low jitter, extremely wide range clock multiplier with precise fractional frequency control and optional spread spectrum capability, giving chip designers the ultimate in performance, features and ease of use.
True Circuits will also showcase its high-performance DDR 4/3 PHY with state-of-the-art tuning and training, and remarkable physical flexibility to adapt to each customer’s die floorplan and package. The DDR 4/3 PHY has been developed using the powerful custom design automation tools that have made TCI’s line of high performance PLLs and DLLs a staple in the semiconductor industry for over 17 years. The availability of this revolutionary PHY means customers can now license a PHY with significant performance and features without all the implementation and timing closure hassles that are common with current DDR offerings.
True Circuits will also feature its complete line of standardized and silicon-proven general purpose, clock generator, deskew, and spread spectrum PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance points, features and foundry processes typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant and reusable. Of particular interest this year is the addition of the TSMC 16nm FF+ and UMC 28nm HLP and HPC processes to our growing portfolio of timing IP.
True Circuits will discuss a number of topics that should be helpful to chip managers and designers, including new standards such as ONFI 4.0, IP selection, IP integration, IP reuse, jitter specifications and silicon testing.
John Maneatis, Ph.D., True Circuits' President and Brian Gardner, True Circuits' V.P. of Business Development, will also make presentations about True Circuits and our Ultra PLL and DDR PHY IP in the ChipEstimate.com booth #2433 each day of the conference.
True Circuits will co-host two parties at DAC again this year, including the LOVE IP Party at Jilian’s on Monday night and the Stars of IP Party at Novela on Tuesday night. Come join us and celebrate all that is good with IP!
When and Where
Moscone Convention Center, San Francisco, CA
True Circuits Booth #2014
Monday - Wednesday, June 8-10, 9:00 AM to 6:00 PM
ChipEstimate.com Booth #2433
Monday, June 8, 2:30 PM
Tuesday, June 9, 4:00 PM
Wednesday, June 10, 4:00 PM
For more information about True Circuits' PLLs and DLLs, please visit www.truecircuits.com.
For more information about the Design Automation Conference, please visit www.dac.com.
About True Circuits Ultra PLLs
The Ultra PLL employs a new state-of-the-art architecture and uses high-speed digital and analog circuits to achieve exceptional performance, with many useful features. It has ultra low jitter (<500fs) for the most demanding SerDes and ADC input clocks. It has ultra wide frequency range with multiplication factors from 3 to over 250,000, supporting reference clocks as low as 32KHz. It also has precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution. It can even generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements. The Ultra PLL packs all these features into a compact size that draws low power and, with full pin programmability, one PLL can be used for all applications on a SoC.
About True Circuits PLLs and DLLs
In addition to the new Ultra PLL, True Circuits offers a complete family of standardized and silicon-proven general purpose, clock generator, deskew, and spread spectrum PLLs and DDR DLLs that spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications. They are pin-programmable, highly process tolerant and reusable. They are also easy to integrate and are fully supported, so customers can reduce both design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication factors and functions over which they deliver optimal performance, avoiding the cost and complexity of licensing multiple point-solution PLLs from foundries or other vendors. TCI's DLLs are available in mutli-slave and multi-phase versions and different sizes and form factors. They delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature and are ideal for high-speed DDR and ONFI interface applications. Customized PLL and DLL solutions are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 16nm. For more information about True Circuits IP products, visit www.truecircuits.com/tci_technology.html and www.truecircuits.com/product_matrix.html.
About True Circuits DDR PHYs
The DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read data eye and gate timing are also continuously adjusted. Automatic training is included for multi-cycle read gate timing and write leveling, write data eye timing, and internal and external (on DRAM) Vref setting.
The PHY employs a localized and optimized PHY-to-memory controller interface to ease timing closure. The circuitry in each pin is able to measure the data eye and jitter, and calculate flight delays. The PHY also includes a full speed read/write BIST, which tests the complete read and write paths of every pin simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer's die floorplan and package constraints, and is delivered and verified as a single unit for easy timing closure with no assembly required. The PHY is also DFI 3.1 compliant, and when combined with a suitable DDR 4/3 memory controller, a complete and fully-automatic DDR 4/3 system is realized.
The True Circuits DDR 4/3 PHY is initially available for customer delivery in TSMC's 28nm HPM/HPC process. The PHY will be available in additional TSMC and GLOBALFOUNDRIES processes in the very near future. Interested customers can obtain more product information on the web at www.truecircuits.com/ddr_phy.html or by contacting True Circuits at email@example.com.
About True Circuits
True Circuits develops and markets a broad range of industry leading PLLs, DLLs and DDR PHY hard macros for ICs for the semiconductor, systems and electronics industries. TCI's robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world's leading foundries, IDMs, and design services companies allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies. Over the last 17 years, True Circuits has distinguished itself as the technology leader in the timing IP space, and its PLLs and DLLs are used extensively around the world in its customers' products with production volumes in the billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los Altos, California 94022 and can be found on the web at www.truecircuits.com. Product inquiries can be made by calling the company directly at (650) 949-3400 or via e-mail at Email Contact.
Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400, Ext. 3404, Email Contact.
Acronyms and definitions:
ASIC Application Specific IC IP Intellectual Property
DLL Delay-Locked Loop ONFI Open NAND Flash Interface
DDR Double Data Rate PLL Phase-Locked Loop
FPGA Field Programmable Gate Array SoC System on a Chip