Atrenta & TSMC Announce Next Generation IP Kit

Expanded Scope of IP Qualification and Metrics

SAN JOSE, Calif. — (BUSINESS WIRE) — June 1, 2015 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries today announced the availability of IP Kit 3.0. The IP Kit is based on the SpyGlass® RTL platform, and for four years, has been a key element of the TSMC9000 soft IP quality assessment (QA) program that helps ensure the highest quality of soft IP blocks.

TSMC’s soft IP QA program is a joint effort between TSMC and Atrenta to deploy a series of SpyGlass checks that create detailed reports of the quality and performance of soft IP across critical domains of design verification. The new IP Kit, based on the SpyGlass 5.4.1 release, improves usability with native Tcl support for an interactive use-model, and is aligned with GuideWare 3.0 – a set of proven checks and best practices for IP design. To date, over 24 IP companies have been qualified as SpyGlass Clean through TSMC’s QA program.

“The soft IP QA program has been providing high quality IP to TSMC’s customers over the last four years,” said Suk Lee, senior director, Design Infrastructure Marketing Division at TSMC. “The new capabilities will provide even more confidence and visibility into the metrics of quality and performance that our customers have come to expect.”

The IP Kit 3.0 has been available for download from TSMC Online starting May 22nd, 2015. The new IP Kit brings a set of new capabilities including:

1) Generation and Management of Timing Constraints (SDC)

2) Power Profiling and Advance Power Optimization

3) Glitch Analysis on CDC Paths

4) Completeness checks for Power Intent (UPF)

5) Physical Lint Analysis

6) Analysis of Multiple IP Configurations

7) Automatic Generation of SpyGlass Abstraction Models (Lint, CDC, DFT, Constraints) to Enable Hierarchical Analysis at the Chip Level

“Atrenta is pleased to continue our collaboration with TSMC in growing the soft IP eco-system,” said Piyush Sancheti, vice president of marketing at Atrenta. “Chip designers are relying on 3rd party IP now more than ever before. With our combined commitments, we are providing a path for a growing number of IP suppliers to significantly increase consumer confidence in the quality of their soft IP.”

About Atrenta Inc.

Atrenta's SpyGlass Predictive Analyzer® significantly improves design efficiency for the world's leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today's consumer electronics revolution. More than two hundred eighty companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. With the addition of GenSys® and BugScope®, RTL modification and verification efficiency are also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.

SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com

© 2015 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass, SpyGlass Predictive Analyzer, GenSys and BugScope are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this release.



Contact:

Atrenta:
Danielle Arnold, 408-453-3333
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