SUNNYVALE, CALIF. – June, 2015 –
Real Intent, known for its blazingly fast, meticulously precise functional verification solutions proven to accelerate RTL verification and sign-off of giga-gate SoC and FPGA designs
Real Intent is once again on the GarySmithEDA What to See at DAC 2015 list and is bringing its advanced Ascent and Meridian technology, EDA expertise and speed-demon fun to the Design Automation Conference (DAC) in San Francisco June 8-10, 2015. In the spirit of faster verification and design success, Real Intent invites attendees to Booth #1422 to:
- Learn the latest information about Real Intent’s
Ascent family of tools for the fastest static RTL verification prior to synthesis and simulation, and its
Meridian tools – including brand new Meridian Physical CDC, a breakthrough in innovation that enables CDC sign-off at the gate level. Meridian solutions deliver faster performance, higher capacity and more precision than any others.
- View technical presentations to get up to speed on Real Intent’s latest advancements, proven on giga-gate SoC and FPGA designs.
here to make an appointment for our suite presentations.
- Complete a quick verification survey to be entered into drawings for a cool
Roku 3 and a
Kindle PaperWhite e-reader.
- Take the wheel of a favorite high-performance race car to celebrate faster verification and design, in one of two
GRID Arcade Racing Simulators, and get a License-to-Speed.
- Visit Real Intent and OpenText (Booth #1414), Real Intent’s “License-to-Speed” partner at DAC; get a ticket stamped by both companies to enter drawings for
Amazon Gift Cards.
- Receive a rose as a sweet thank-you gift.
Real Intent also invites attendees to Room #304 to
- View Scalable Verification: Evolution or Revolution? – a stimulating pavilion panel on Wed., June 10 from 4:30-6 p.m. Co-organized by Real Intent, this panel is moderated by Brian Bailey, technology and EDA editor of Semiconductor Engineering. Experts from Freescale Semiconductor, NVIDIA, Qualcomm, Hewlett-Packard and ARM will discuss whether existing industry verification standards and methodologies for verifying IP blocks and subsystems can be extended to address SoC integration and system-level functionality of embedded systems, or if new approaches are needed.
The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors.
Mon. & Tue., June 8, 9 10 a.m. – 7 p.m., Booth #1422
Wed., June 10 10 a.m. – 6 p.m., Booth #1422
Wed., June 10 4:30 – 6 p.m., Room #304
At the Moscone Center
747 Howard St.
San Francisco, CA 94103
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
RTL: Register Transfer Level
Real Intent and the Real Intent logo are registered trademarks, and Ascent, iDebug and Meridian are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
Sarah Miller for Real Intent
ThinkBold Corporate Communications