MathWorks Introduces Pixel-Streaming Algorithms for Design and Implementation of Vision Systems on FPGAs and ASICs

New Vision HDL Toolbox shortens concept-to-design cycles and identifies design errors early in the design workflow

NATICK, Mass. — (BUSINESS WIRE) — May 7, 2015 — MathWorks today introduced Vision HDL Toolbox, a new product now available in the company’s Release 2015a. Vision HDL Toolbox provides pixel-streaming algorithms for the design and implementation of vision systems on FPGAs and ASICs. The toolbox also includes a design framework that supports a diverse set of interface types, frame sizes, and frame rates, including high-definition (1080p) video. The image processing, video, and computer vision algorithms in the toolbox use an architecture appropriate for HDL implementations.

Vision algorithm developers are challenged by the combination of increasing video frame sizes, frame rates, and the complexity of prototyping or implementing the vision algorithms on FPGA and ASIC platforms. Vision HDL Toolbox helps developers overcome these challenges by providing a library of image processing and computer vision algorithms specifically designed for FPGA and ASIC implementation, as well as automatic conversion between frames of various sizes and pixels. In addition, when used with HDL Coder, designers can generate readable and vendor-independent HDL code from these algorithms. And, with HDL Verifier, designers can connect the algorithms running on the FPGA or ASIC with frame-based test models running in MATLAB or Simulink.

“FPGAs in particular are an increasingly popular platform for image processing and computer vision systems,” said John Zhao, marketing manager at MathWorks. “The new Vision HDL Toolbox has been created to help developers prototype and implement systems faster, with shortened design cycles, and more efficiently, through the ability to identify design errors early in the workflow and minimize the time needed for writing HDL code.”

Key Vision HDL Toolbox Features

  • Image processing, video, and computer vision algorithms with a pixel-streaming architecture, including image enhancement, filtering, morphology, and statistics
  • Frame-to-pixel and pixel-to-frame conversions to integrate with frame-based processing capabilities in MATLAB and Simulink
  • Video synchronization signals for handling nonideal timing and resolution variations
  • Configurable frame rates and frame sizes, including 60FPS for high-definition (1080p) video
  • Support for HDL code generation and real-time verification

For pricing and more information, see Vision HDL Toolbox. This product is available immediately worldwide.

About MathWorks

MathWorks is the leading developer of mathematical computing software. MATLAB, the language of technical computing, is a programming environment for algorithm development, data analysis, visualization, and numeric computation. Simulink is a graphical environment for simulation and Model-Based Design of multidomain dynamic and embedded systems. Engineers and scientists worldwide rely on these product families to accelerate the pace of discovery, innovation, and development in automotive, aerospace, electronics, financial services, biotech-pharmaceutical, and other industries. MathWorks products are also fundamental teaching and research tools in the world’s universities and learning institutions. Founded in 1984, MathWorks employs more than 3000 people in 15 countries, with headquarters in Natick, Massachusetts, USA. For additional information, visit mathworks.com.

MATLAB and Simulink are registered trademarks of The MathWorks, Inc. See mathworks.com/trademarks for a list of additional trademarks. Other product or brand names may be trademarks or registered trademarks of their respective holders.



Contact:

Press Contact
MathWorks
Len Dieterle, 508-647-4404
Email Contact




Review Article Be the first to review this article
Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Simon Davidmann: A re-energized Imperas Tutorial at DAC
Peggy AycinenaIP Showcase
by Peggy Aycinena
ARM: A Gnawing Sense of Unease
More Editorial  
Jobs
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
LVS for PDK Design Engineer SILICON VALLEY for EDA Careers at San Jose, CA
DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA
LVS PEX DESIGN ENGINEERS SILICON VALLEY for EDA Careers at San Jose, CA
Upcoming Events
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
DVCon India 2017, Sept 14 - 15, 2017 at The Leela Palace Bengalore India - Sep 14 - 15, 2017
SMTA International 2017 at Rosemont IL - Sep 17 - 21, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy