Credo First to Demonstrate 28G SerDes on 16FinFET Plus Technology

Leads the Industry with First Public Demonstration at TSMC Symposium

Milpitas, Calif. and Shanghai, China, May 6, 2015 – Credo Semiconductor, a global innovation leader in Serializer-Deserializer (SerDes) technology, today announced it is the first company to deliver silicon-proven 28G NRZ SerDes IP on the TSMC 16-nanometer FinFET Plus (16FF+) process, and will demonstrate its high-performance, low power characteristics at the TSMC Symposium this week in Shanghai, China.  Credo is also demonstrating its 28G SerDes at 28-nm, also available now, and providing a preview in silicon of a new 56G SerDes using PAM-4 signaling.  The solutions will be on display in Booth B-10.

The new 16FF+ 28G SerDes is immediately available to designers targeting chip-to-module, chip-to-chip, and chip-to-fabric applications.  ASIC, ASSP and SoC designers must move to more advanced process technologies in order to address the rising bandwidth and performance demands driven by enterprise, data center and high-performance computing applications.

“This demonstration delivers on our commitment to establish technology leadership in SerDes IP so that our customers can deliver their own compelling networking solutions and pave the way to 100G and 400G networks,” said Bill Brennan, CEO of Credo Semiconductor.  “Perhaps even more important than being first to market, though, is our ability to continue to drive down power, while maintaining the best reach, noise immunity and jitter performance in the industry.”

“This is a significant milestone – not just for Credo, but for the industry,” said Bob Wheeler, principal analyst at The Linley Group.  “The combination of 16FF+ with 28G SerDes technology is critical to enabling the high-density ASICs required for 400G port speeds and Terabit line cards."

The 16FF+ 28G SerDes will enable solutions that support industry standards including CEI-25G-SR, CEI-25G-MR and CEI-25G-LR, with insertion loss performance with 40dB class requirements. It also supports the IEEE 802.3bj standard defining 100G transmission over backplanes and copper cables.

The Credo 28G SerDes delivers random jitter performance of less than 120 fs.  Further, the Credo 28G features unique Rx auto-adaptation which eliminates the need for post-silicon tuning and/or firmware updates and release management, excellent supply noise rejection, and a wide range of Rx input common mode tolerance – all of which simplify system-level , board-level, and chip-level integration.

Availability

The Credo 28G SerDes IP is available now.  Credo supports its IP with comprehensive documentation, modeling, layout and verification information.  Deliverables include user and integration guides; netlist; timing library; register map; Verilog, ATPG, and IBIS-AMI models; Layout Versus Schematic (LVS) and Design Rule Check (DRC) reports. 

Companies interested in learning more about the company’s current silicon and intellectual property engagement options, as well as future developments should contact Email Contact.



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