Real Intent at DVCon 2015: Verification Solutions and Roses in Booth #602

SANTA CLARA, CALIF. – Feb. 26, 2015 –

Who

Real Intent, whose advanced functional verification solutions accelerate electronic design sign-off, eliminate complex failures in systems-on-chip (SoCs), and lead the market in performance, capacity, accuracy and completeness 

What

Will exhibit its Ascent and Meridian productsin Booth #602 at the 2015 Design & Verification Conference & Exhibition ( DVCon 2015) next week. Visitors to Booth #602 also will receive a rose from Real Intent – a sweet tradition for two years now. DVCon, which typically attracts more than 800 attendees, is the premier industry conference for design and verification engineers of all experience levels, and for engineering managers.

Real Intent’s Ascent products provide the fastest early functional verification for clean RTL before simulation and synthesis.  They find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, improving QoR and productivity for design teams. Comprehensive low-noise reporting makes debug fast and efficient for linting, X-verification and optimization. The new version of Ascent Lint with DO-254 compliance testing addresses the needs of companies developing next-generation designs for FPGAs or complex SoCs. It helps ensure that designers’ airborne electronics meet the industry standard for quality and reliability. 

Real Intent’s Meridian products accelerate sign-off verification of clock domain crossings and SDC in billion-gate SoC designs. This breakthrough technology delivers unmatched speed, capacity, precision and low-noise reporting. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC or FPGA devices are received reliably. Meridian CDC is the only solution that enables all aspects of CDC sign-off. Meridian Constraints is the best-in-class, comprehensive constraint management solution in the market.

DVCon is sponsored by Accellera Systems Initiative, an independent organization dedicated to providing design and verification standards required by systems, semiconductor, intellectual property (IP) and design tool companies to enhance a front-end design automation process.  

When/Where

DVCon Expo Booth Crawl

Monday, Mar. 2, 5-7 p.m. - food and drink provided

DVCon Expo Exhibit

Tuesday, Mar. 3 and Wednesday, Mar. 4 from 2:30-6:30 p.m. at the Doubletree Hotel, San Jose, Calif.

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and sign-off of electronic designs. Real Intent’s comprehensive CDC verification and advanced RTL analysis eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.

Real Intent and the Real Intent logo are registered trademarks, and Ascent, Meridian and iDebug are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners. 

Press contact:
Sarah Miller for Real Intent
ThinkBold Corporate Communications
231.264.8636
sarah@thinkbold.com




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