Verific Design Automation Closes Fifth Consecutive Year of Growth

ALAMEDA, CA -- (Marketwired) -- Jan 20, 2015 -- Verific Design Automation, provider of SystemVerilog, VHDL and UPF parsers, finished its fifth consecutive year of growth with a double-digit increase in revenue.

In 2014, Verific added eight new customers, such as Flexras, recently acquired by Mentor Graphics, Invionics and Menta. They join a list of longtime customers that includes the largest electronic design automation (EDA) companies, field programmable gate array (FPGA) vendors and integrated device manufacturers (IDMs) who recognize Verific for its quality Parser Platform. Sample customers are Aldec, Altera, AMD, Atrenta, Cadence Design Systems, Lattice, Mentor, Microsemi, NVIDIA, Real Intent, Synopsys, Tabula and Xilinx.

Verific also continued its history of ongoing technology R&D with the introduction of its UPF 2.1 (IEEE 1801-2013) parser. In addition, it released its Hierarchy Tree project, a lightweight static elaborated layer on top of an analyzed SystemVerilog or VHDL parse tree.

"Companies know our 15-year history of building and testing parsers used in many production environments and that translates into having the confidence to work with us," says Michiel Ligthart, Verific's president and chief operating officer. "Over the years, we've built a foundation of trust through quality products and top-notch support, which is why companies continue to renew their licenses each year."

Verific's software serves as the front end to a wide range of EDA and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Verific's Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: Website:

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact:
Nanette Collins
Public Relations for Verific 
(617) 437-1822 

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