Real Intent to Exhibit at 28th International Conference on VLSI Design in Bangalore

BANGALORE – Dec. 18, 2014 –  


Real Intent, whose RTL verification solutions accelerate electronic design sign-off, eliminate complex failures in SoCs, and lead the market in performance, capacity, accuracy and completeness


Will exhibit its breakthrough Ascent and Meridian productsat the 28th International Conference on VLSI Design (VLSID) in Bangalore, India on Jan. 5-7, 2015, through its distribution partner Claytronics Solution, also known as Claysol. Real Intent’s Ascent products provide the fastest early functional verification for clean RTL before simulation and synthesis; its Meridian products deliver unmatched speed, capacity and low-noise reporting to speed sign-off verification of clock domain crossings and SDC in giga-gate SoC designs.

The annual VLSID conference is the only event in India dedicated solely to the VLSID ecosystem. It typically attracts more than 1,000 industry, academia, researchers, innovators  and regulators from across the globe to exchange useful information on current topics in VLSI design, electronic design automation, electronic system design and enabling technologies. The venue includes presentation sessions, exhibits, panel discussions and a user forum.


Jan. 5-7, 2014

The Leela Palace Bangalore
#23, Kodihalli, Old Airport Road
Bangalore 560 008
T. +91 (80) 2521 1234

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit for more information.

Real Intent and the Real Intent logo are registered trademarks, and Meridian and Ascent are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.


CDC       Clock Domain Crossing
EDA        Electronic Design Automation
RTL        Register Transfer Level
SDC        Syopsys Design Constraints
SoCs      Systems on Chip
VLSI       Very Large Scale Integration

Press contact:
Sarah Miller for Real Intent
ThinkBold Corporate Communications
Email Contact

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