Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification

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SAN JOSE, Calif., Dec. 11, 2014 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced the Cadence® Perspec System Verifier platform for use-case scenario-based software-driven system-on-chip (SoC) verification. Using an intuitive graphical specification of system-level verification scenarios and a definition of the SoC topology and actions, this new verification solution automates system-level coverage-driven test development using constraint-solving technology, delivering up to 10X productivity improvement in SoC verification versus typical manual test development. A part of the Cadence System Development Suite, Perspec System Verifier reduces complex test development from weeks to days, while also allowing design teams to reproduce, find and fix complex bugs to improve overall SoC quality.

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Perspec System Verifier is currently available. For more information, visit http://www.cadence.com/news/perspec.

Perspec System Verifier delivers increased productivity and SoC quality through several key features, including:

  • A Unified Modeling Language (UML) based view of system-level actions and resources that, combined with powerful solver technology, creates an intuitive view of complex and hard-to-test system-level use-case interactions
  • Solver technology, which automates the generation of portable tests to deliver complete coverage of system-level scenarios based on chip constraints and the scope of the scenarios to verify SoC-level features for functionality, performance and power
  • Tests that run on all pre-silicon verification platforms including simulation, acceleration and emulation, and virtual and FPGA prototyping, which can be further used to validate actual silicon

"Today's verification teams face a challenge in that the bottom-up approach to IP verification does not extend to the SoC level, and they are looking for an opportunity to move to top-down scenario-based verification in order to extend traditional approaches like UVM and achieve better coverage," said Charlie Huang, executive vice president, Worldwide Field Operations and System & Verification Group at Cadence. "With its SoC-level constraint-solving technology, Perspec System Verifier is enabling our customers to create tests previously not feasible, increasing their confidence that they are meeting SoC functional requirements while speeding time to market."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.

© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
408-944-7039
Email Contact

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To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/cadence-perspec-system-verifier-delivers-up-to-10x-productivity-improvement-in-system-on-chip-verification-300007283.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com




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