Plunify's InTime Design Optimization Software Supports Altera FPGAs and SoCs

LOS ALTOS, CA -- (Marketwired) -- Nov 12, 2014 -- Plunify® Pte. Ltd., provider of groundbreaking field programmable gate array (FPGA) software, today announced its InTime™ design optimization software provides support for Altera's FPGAs and systems on chip (SoCs).

Plunify's InTime software harnesses computing resources and machine learning to rapidly generate optimized strategies for solving design problems.

"We are pleased to have Plunify join our partner network," says Alex Grbic, director of software and IP marketing at Altera. "Working with companies like Plunify enables us to offer our customers a variety of complementary solutions."

Plunify's InTime software can provide Altera users a faster path to production. The InTime design optimization software evokes Altera's Quartus® II software to analyze designs and determine the best synthesis and place-and-route strategies. InTime has built-in intelligence to examine an FPGA design, derive correlations between the design, the FPGA device and the tool parameters, and subsequently provide users optimized strategies for synthesis and place-and-route. In one example, Huawei successfully deployed InTime in its production flow to close timing on multiple designs.

Introduced in June, InTime uses statistical modeling and machine learning to draw insights from the data to improve quality of results. Furthermore, InTime has the ability to accumulate knowledge that can be applied to subsequent designs, or re-applied to the same design after it has been modified.

"We are pleased to be part of the Altera ecosystem," remarks Harnhua Ng, Plunify's chief executive officer. "The evaluations we did with mutual customers and the benchmarking results show that InTime can be a valuable solution to analyze and manage multiple FPGA design compiles. Users appreciate InTime's machine learning feature because the engine gets better each time they run it."

About Plunify
Solutions from Plunify® Pte. Ltd. enable semiconductor chip designers to shorten product time to market and reduce development costs with no disruption to existing workflows. Its EDAxtend™ cloud platform and InTime™ timing closure tool help electronics companies meet FPGA design performance targets and significantly reduce their products' time to market. For more on Plunify's products, visit www.plunify.com.

Plunify is a registered trademark of Plunify Pte. Ltd. EDAxtend is a trademark of Plunify. Plunify acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact:
Nanette Collins
Public Relations for Plunify
(617) 437-1822

Email Contact





Review Article Be the first to review this article
CST Webinar Series

EMA:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Retail Therapy: Jump starting Black Friday
Peggy AycinenaIP Showcase
by Peggy Aycinena
REUSE 2016: Addressing the Four Freedoms
More Editorial  
Jobs
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
RELIABILITY ENGINEER... FRANCE for EDA Careers at FRANCE, France
Technical Support Engineer for EDA Careers at Freemont, CA
Upcoming Events
Zuken Innovation World 2017, April 24 - 26, 2017, Hilton Head Marriott Resort & Spa in Hilton Head Island, SC at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy