In the design phase of a chip, IP typically comes from internally developed or 3rd party IP providers. The IP is then integrated into the architecture to functionally perform the task needed by the end application. These can be complicated IP like DDR, Serdes, PLLs, memories, CPUs, etc. They can also be simple IP such as voltage monitors or temperature monitors to check the fab process. In a large customer chip or SOC, you can imagine dozens, or even hundreds, of pieces of IP sprinkled throughout the chip.
A huge task for any chip verification team is to develop all the tests and the testbench to verify all of these pieces of IP in the SOC. Typically, they would have to figure out how to stimulate these IP and then observe something to indicate if the IP works or not. This could be some type of functional test, Built In Self Test (BIST) or loopback test, CPU based test, etc. They’ll need knowledge of that specific chip architecture and how each IP should work. In many cases, these verification tests may need to be driven and observed from the chip pins in simulation so manufacturing tests can be developed from the resulting evcd file(s).
Certainly scan and BIST (Built In Self Test) based testing has helped significantly to make sure the manufactured digital logic is of good quality. However, you still have the big issue of how to connect to these structures, control them, and get failing data out, and how to control the start and stop of these tests.
For IP that might be timing sensitive or mixed signal, other types of verification and testing may still be needed in both the simulation and the ATE tester world.
Wouldn’t it be nice to reuse the original IP provider’s original verification and test suites to make sure all of your IP works and was manufactured correctly? Correct not only for simulation, but for ATE test, Board Test, System Test, and possibly in field testing as well. Now you’re talking about an entire eco-system from design to application.
Wouldn’t it also be nice to have a network that could be reconfigurable to get to and from all of these different pieces of IP in any order you like? This would allow you, for instance, to optimize which manufacturing tests are run, and in which order based on test time, power, etc. All while minimizing test time by not having to access every IP on every scan frame.
Furthermore, wouldn’t it be nice to not have to develop a testbench with all the simulation and have it auto-generated for you?
Still better, wouldn’t it be nice to get ATE patterns directly out of the same process without having to use additional tools to convert simulation to ATE patterns?
Finally, wouldn’t it be nice to be able to use this same common technique and methodology across different products within your company? A common test methodology would give the user the ability to standardize on a common test interface and common reusable test controllers to optimize flow, equipment, training, etc.
These issues and more can be addressed by using these two new standards.
The Bloody Crusades of Embedded IP TEST
Because there is overlap between the new 1149.1-2013 and the P1687 standards, the obvious question is, “Which one is superior?”. Though a better question could be, “Which standard better fits my goals and architectural requirements with the time and resources we have?”. IEEE 1149.1 is still the standard for traditional board test. Your board-mountable components will still rely upon it. However, the overlap between the two standards has a lot of people confused. If you take a step back, it becomes obvious that each can have a place in our new plug and play, automated, reusable world of embedded test capabilities. Both can also leverage integration, verification, ATE test, and validation within chips, within boards, and within systems.
Both standards have a few common basic ideas:
- Support of a reconfigurable network to access test capabilities
- Reuse of IP level patterns at chip, board, and system
- Standard JTAG test interface
It is important to remember that each standard has its own strengths, as well as slightly different input requirements. In future articles, we’ll discuss how you might decide which best fits your needs for a specific device and its goals.
Eventually, the industry will sort out which standard is most useful in which situations, but in the meantime, there is already a bit of a “religious” debate building around this question. Many IP and components may profit from supporting both standards until the debate is settled. The information to do so already exists, and in most cases, simply needs to be formatted in the languages specified by the two standards. We may indeed find that in the designs of tomorrow, we have a mix of IP from multiple sources and some are 1149.1-2013 based, some are P1687 based, and some will support either.
It is clear that both of these standards will affect you in the coming year or so if you are apart of the semiconductor industry. This is especially true of those of you who are in IP development, chip design, verification, integration, test, validation, board test, applications, or system development. Don’t wait around to get involved. Now is the time to get on board before this train leaves you behind!
Be watching for our next article in the series coming out soon!
Full Disclosure About SiliconAid Solutions Inc.
SiliconAid has contributing members in the following IEEE working group: 1149.1-2013, P1687, and IEEE 1149.6. SiliconAid provides a full suite of chip focused products to support P1687, 1149.1, and 1149.6 standards. (IE. We are not a board test focused company. We are a JTAG based standards chip focused company.)
SiliconAid Solutions, Inc. is recognized as a leading provider of Design for Test consulting services encompassing methods, implementation, as well as team augmentation and training. The Senior DFT Consulting Group has been recognized for comprehensive support of all standard EDA DFT solutions.
SiliconAid also delivers world class chip-focused JTAG software solutions to validate, verify, and utilize IEEE 1149.X and P1687 related industry standards. The exhaustive chip-level validation, verification, and debug of IEEE JTAG-compliant implementations is based on over 20 years of testing and thousands of designs from multiple satisfied worldwide semiconductor companies. SiliconAid has corporate headquarters located in Austin, Texas and was founded in 2001.