The market segments range from broadband, cellular communications and DSL to high definition TV (HDTV), image processing, networking, test and measurement and video equipment. Each company selected Uniquify's DDR memory subsystem IP for its innovative adaptive technology -- self-calibrating logic (SCL) and dynamic SCL (DSCL) for real-time static and dynamic timing calibration.
"Design teams worldwide and in all market segments have found a huge competitive advantage when licensing our DDR memory IP," remarks Josh Lee, Uniquify's chief executive officer, a leading high-performance semiconductor IP and system-on-chip (SoC) design, integration and manufacturing services supplier. "It's both high performance and low power, two compulsory characteristics needed for SoC design."
SoC designs integrate DDR memory IP that operate at multi-GHz clock rates with read-write timing margins measured in picoseconds. Designing the DDR memory IP to accommodate variations in system-level timing parameters during read and write cycles can require exhaustive rounds of incremental tuning that can cause suboptimal system yield in volume production.
Uniquify's SCL technology solves this problem by performing automatic self-calibration at system power-up for optimal DDR interface timing. SCL-enhanced DDR memory IP offers higher yield because it automatically adapts critical timing characteristics for a wide range of system-level design choices and for variations in the SoC and DDR memory processes.
The DSCL technology builds on SCL by extending the precise timing calibration to execute dynamically during system operation. This is how a 28nm DDR4 system was able to achieve performance of 2800Mbps when operating with an SDRAM rated for 2400Mbps operation. During system operation, temperature and supply voltages vary over time, degrading DDR memory performance and causing potential intermittent memory subsystem failure.
DSCL automatically re-calibrates the critical DDR memory interface timing at user-specified intervals during system operation and is set to operate during periods of low memory activity for negligible impact on system throughput. The DSCL calibration is fast and the hardware required to support the addition of DSCL is minimal. In fact, the addition of DSCL results in a smaller DDR PHY since it obviates the need for other synchronizing hardware that is required in the traditional (non-DSCL) PHY architecture such as FIFOs.
Uniquify is a rapidly growing system-on-chip (SoC) design, integration and manufacturing services supplier, and innovative developer of high-performance semiconductor intellectual property (IP) offering the world's fastest DDR memory IP. Its "ideas2silicon" services range from specification development and front-end design through physical design and delivery of packaged, tested chips. It offers 65-, 40- and 28-nanometer SoC design expertise, integration and manufacturing services to leading semiconductor and system companies worldwide. Uniquify's adaptive DDR subsystem IP offers the highest DDR performance with the lowest power, smallest area and the best system reliability -- a result of its patented self-calibrating technology. Uniquify's headquarters and primary design center is in San Jose, Calif., with additional design and technical sales and support teams in China, India, Japan, Korea and Vietnam. For more information, visit: www.uniquify.com.
ideas2silicon is a trademark of Uniquify. Uniquify acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
For more information, contact: Bob Smith Uniquify (650) 269-8780 Email Contact Nanette Collins Public Relations for Uniquify (617) 437-1822 Email Contact