Menta Origami Designer Used to Create Embedded FPGAs in SoC Designs
ALAMEDA, CALIF. –– July 2, 2014 –– Verific Design Automation today announced Menta® selected its industry-standard, IEEE-compliant SystemVerilog and VHDL parsers to serve as the front end to Menta Origami Designer™ used to create embedded FPGAs (eFPGAs) for system-on-chip (SoC) designs.
“Menta brings a unique approach to embedded FPGA architectures, and follows in the footsteps of the entire FPGA industry by selecting Verific as its front end,” says MichielLigthart, Verific’spresident and chief operating officer. “We take great pleasure in supporting Menta’s forward-thinking approach.”
Menta Origami Designer automates the design and implementation of Menta’s flexible and customeFPGA intellectual property (IP), defining, analyzing and validating the target capacity, performance, interconnect density and programming for the target device.
“As an innovative company, Menta needs to carefully select its partners and suppliers,” comments Laurent Rougé, Menta’s founder and chief executive officer. “Verific has proven to be the best EDA partner and supplier anycompany can hope to work with, offering first-rate technology and outstanding support.”
Verific’s software is the front end to electronic design automation (EDA) and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl APIs. Verific’s software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.
Menta is a privately held company based in Montpellier, France. The company provides embedded FPGA (eFPGA) technology for system on chip (SoC), ASIC or system in package (SiP) designs, from EDA tools to IP generation. Menta’s programmable logic architecture is based on scalable, customizable and easily programmable architecture created to provide programmability for next-generation ASIC design with the benefits of FPGA design flexibility. For more information, visit the company website at: www.menta-efpga.com.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email:
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