ASIC design experts to present techniques for multi-million block implementation
eInfochips, a leading product and semiconductor design company will deliver a presentation at the prestigious Silicon Valley leg of the Cadence User Conference series - CDN Live 2014 - on Wednesday, March 12th. One of the few elite engineering teams selected to present at the event, eInfochips will address a complex topic that is rarely covered: a highly congested, hierarchical design with memory and I/O that need careful planning of logic grouping and placement of I/O.
"We have codified our experiences on the physical design challenges for technology nodes as low as 16nm." said Parag Mehta, the Chief Marketing and Business Development Officer at eInfochips. "The CDN Live forum is the ideal platform to share our experiences, and learn from others." he added.
The paper, titled "Floor-plan Challenges for Physical Implementation of multi-million blocks" will cover the intricacies of layout implementation, including critical routing and timing requirements. The paper also covers the challenges the team faced during some complex projects, and approaches to counter them using the Cadence SoC Encounter solution.
About CDN Live
CDN Live is the annual Cadence User Conference where design engineers come together to connect, share and inspire. The conference attendees are Cadence technology users, developers, and industry experts who do this by networking, sharing best practices on critical design and verification issues, and by discovering new techniques for developing advanced silicon, SoCs, and systems.
eInfochips is a global product innovation partner recognized for technology leadership by Gartner, Frost & Sullivan, NASSCOM and Zinnov. eInfochips has contributed to 500+ products for top global companies, with more than 10 million deployments across the world.
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