Calypto Design Systems to Showcase Solutions Ranging from Low-Power RTL Design to C Based Design & Verification at DVCon 2014

SAN JOSE, Calif. – February 26, 2014 – Calypto® Design Systems, Inc., the leader in low-power RTL design and C-Based design and verification, announced it is demonstrating its Catapult®, PowerPro®, and SLEC® products at DVCon 2014, a three-day exhibit at the Double Tree Hotel in San Jose, CA. Used by the world’s leading system and semiconductor companies, Calypto’s family of products enable ASIC, SOC, and FPGA designers of today’s most innovative electronic products to quickly create fully-verified, power-optimized RTL for downstream synthesis and physical design.

WHO:

Calypto Design Systems

WHAT:  

Calypto will exhibit and provide demos for its Catapult, PowerPro, and SLEC products.  Catapult High-Level Synthesis products give designers the option to use SystemC or C++ to dramatically shorten the design cycle by producing correct-by-construction, error-free, power optimized RTL. The PowerPro product line enables users to analyze both static and dynamic power usage at the RTL and either automatically or manually create low-power RTL that includes memory and leakage power optimization. The SLEC family of products formally verifies RTL without the need for time consuming simulation and complex testbenches. The end result is a dramatic reduction in time to market and up to 60% reduction in power.

WHEN:

Monday, March 3 from 5:00 PM – 7:00 PM

Tuesday, March 4 and Wednesday, March 5 from 2:30 PM – 6:00 PM

WHERE:

DVCon 2014

Double Tree Hotel - 2050 Gateway Pl, San Jose, CA 95110.

Calypto Booth #804

About DVCon:

The DVCon 2014 Expo continues to be the premier conference for design and verification engineers of all experience levels. It is a unique opportunity for attendees to learn about technology solutions and innovations, identify cutting-edge technologies, and evaluate products side-by-side to help optimize designs and accelerate time-to-market launches. For details and registration visit: http://dvcon.org/

About Calypto:

Calypto® Design Systems,Inc. is the leader in ESL hardware design and RTL power optimization. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, and Si2. Calypto is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.




Review Article Be the first to review this article
CST: Webinar October 19, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
FPGA Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Upcoming Events
Preparing for the Cognitive Era: Education, Occupation and You at SJSU Student Union Theater 211 South 9th Street San Jose CA - Oct 18, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise