AWR Announces Analog Office 2004 Next-Generation Analog & RFIC Design System

New Version Enhances Openness and Boasts Seamless Integration With Popular Industry Tools for Complete Analog and RFIC Design

EL SEGUNDO, Calif. - May 17, 2004 - Applied Wave Research, Inc. (AWRTM) a leading provider of high-frequency electronic design automation (EDA) tools, today announced Analog OfficeTM 2004 software for next-generation analog and radio-frequency integrated circuit (RFIC) designs. This latest version of the Analog Office solution, which is the first complete IC design system in over a decade that is specifically architected and optimized from the ground up for designers of analog and RF ICs, has been enhanced to provide the industry's most open, unified design environment, offering full interaction with a comprehensive and powerful set of integrated tools. The Analog Office 2004 toolset spans the entire IC design flow, from system-level to circuit-level design and verification, for complete top-to-bottom and front-to-back high-frequency design. AWR will be showcasing the Analog Office design suite at the Design Automation Conference (DAC) June 7 - 9 in San Diego, booth #4043.

New in the Analog Office 2004 product is: support for the Linux platform, a significant extension of the AWR Intelligent Net™ (iNet) technology to handle arbitrary layout geometries; automatic and "on the fly" connectivity extraction in layout; support for Verilog-A analog behavioral language; integration of an additional SPICE circuit simulator and electromagnetic (EM) simulators; and support for industry standard physical verification flow for final chip tape-outs.

"The complexity of today's new technologies renders traditional design methods inadequate in terms of accuracy, efficiency and cost. An entirely new EDA approach is required in order to ensure complete design closure between IC, package, module, and PCB design phases," said James Spoto, AWR president and CEO. "The Analog Office design system provides the ability to achieve optimum RF closure through a unified data model and single design environment encompassing all of the design domains."

RF Closure and Unified Data Model
The high-frequency impairment challenges in today's complex RFICs are forcing the need to obtain "RF closure" between the RFIC's system and circuit, electrical and physical, and design and test activities before commitment to costly IC implementation. The Analog Office design system provides an entirely new design approach that achieves optimum RF closure through a unified data model and a unique design environment. The AWR Design Environment™ is built on an open, standards-based software platform, enabling easy integration of the most capable, best-in-class tools to capture, synthesize, simulate, optimize, layout, extract, and verify designs in all domains. This protects customers' investment in models and simulators, lowers their cost of support, and facilitates easy customization of specific flow requirements.

Complete Front-to-Back Analog and RFIC Design System
The Analog Office unified design environment fully interacts with a comprehensive and powerful set of integrated tools, including:

  • Easy-to-use graphical user interface (GUI) supporting
    • System-level and circuit-level design methodologies
    • Electrical and physical design, schematic capture, simulation/analysis, and layout and verification
    • Frequency- and time-domain simulation and analysis
    • Links from design to test
  • Integrated waveform display & analysis capabilities supporting complex RF measurements
  • Support for different types of simulation
    • System simulation with Visual System Simulator™ (VSS) design suite
    • Time-domain simulation with Synopsys' HSPICE™
    • Frequency-domain simulation with AWR's harmonic balance simulator
    • EM simulation with AWR's EMSight™ software tool
  • Open platform for third-party tool integration
    • SPICE socket for third-party SPICE-based circuit simulators
    • EM socket for third-party EM simulators
  • Powerful and easy-to-use physical design suite
    • Fully interactive layout editor supporting polygon editing and parameterized layout cells
    • Automated device-level placement and interconnect routing
    • Integrated and interactive design rule checker (DRC)
    • 3-D full field solver-based extraction with industry gold standard, high-speed extraction technology from OEA International
Coupled with industry leading semiconductor foundry design kits for silicon germanium (SiGe), and RF complementary metal-oxide semiconductor (CMOS) processes as well as gallium arsenide (GaAs), Analog Office software is the first completely new system in over a decade delivering concept-to-verification design capabilities.

Measurement-Driven Paradigm
Analog Office 2004 design suite has pioneered a new, yet more natural, paradigm for high-frequency design. In traditional EDA systems, users must undergo multiple design setup steps to obtain a particular analysis result from a selected simulator, resulting in the generation of many data files. In the Analog Office product, however, users simply set up multiple test benches and analysis measurements ahead of time (similar to a specification sheet) and then set up the parameters for the designs. As soon as the simulation is started, the system automatically: selects the "right" simulator for the particular analysis, extracts the "right" models for the design elements, runs the simulator(s), obtains the results and processes them into requested measurements, and presents the results in multiple graphs and tables. In the same environment, users can dynamically "tune" the design across a set of parameters, test benches, and simulators very quickly and efficiently. The Analog Office measurement-driven paradigm significantly improves the productivity of the RF design process.

Physical Layout with Automatic Placement and Routing, Integrated DRC and Embedded 3-D Extractor

The Analog Office package offers a fully interactive custom layout tool with integrated device-level, auto-placement, and auto-routing features to speed the creation of analog and RF circuit blocks and chips. An integrated DRC ensures that the physical layout being created always meets the process design rules, resulting in a correct-by-design, error-free layout. The layout editor is directly connected to the EM socket, providing "on the fly" EM extraction and modeling of arbitrary layout structures and complex spiral inductors. At every step during the physical design process, the iNet technology continuously updates in real time the underlying interconnect data model, and as soon as each interconnect is implemented or laid out, concurrent simulation and analysis can be immediately invoked on the schematic or layout. This verifies the performance without waiting for completion of the final layout of the entire design.

To ensure proper modeling of inductance coupling between nets in gigahertz physical layout, the Analog Office design system also integrates the interconnect extraction technology from OEA International's NET-AN™ 3D critical multi-net field simulator. The selected net or nets are automatically extracted and modeled as distributed resistance, capacitance, inductance and mutual inductance (RLCK) for fast and accurate simulation. This level of interconnect modeling compliments other modeling levels that are managed by the iNet technology, such as lumped RLCs, and fully distributed transmission lines, thus extending the range of design trade-off flexibility between simulation run-time performance and modeling accuracy.

Seamless Integration with Industry-Leading Mixed-Signal IC Design Flows
Analog Office 2004 design suite can be used to design the entire chip from system-level modeling and simulation through to final layout and tape-out. The software will generate the necessary industry-standard files, such as layout-versus-schematic (LVS) netlist, and GDSII, to interface to a final verification flow based on industry-popular IC physical verification tools from Mentor Graphics, Synopsys, and Cadence.

The Analog Office software can also be used to design complete RF blocks as part of a large mixed-signal systems-on-chip (SoC). In this flow, AWR provides complete, bidirectional data transport capabilities to and from industry standard mixed-signal IC design flows.

Price and Availability
AWR will release Analog Office 2004 design suite to customers in Q3 2004. The product supports Windows NT4, 2000, XP, and Linux. U.S. list prices for yearly, time-based licenses range from $8,000 - $40,000 depending upon configurations. For more information on product pricing and availability call 310-726-3000. For product pricing and availability outside the U.S., please contact AWR or AWR's local sales representative.

About Applied Wave Research, Inc.
Applied Wave Research is a leading supplier of high-frequency electronic design automation (EDA) products for the design of wireless telecommunications equipment, semiconductors, high-speed computers, networking systems, and a variety of other electronics-based products. AWR is a privately held company and has development offices, sales offices, training centers, and global distribution. AWR launched its first product in 1998 and today has over 400 customer companies worldwide, including virtually every major high-frequency electronic component and system supplier. The company is located at 1960 East Grand Avenue, Suite 430, El Segundo, California 90245. For more information about AWR and its products, please visit or call 310-726-3000.

AWR, the AWR logo, Analog Office, Visual System Simulator, AWR Design Environment, Intelligent Net, and EMSight are trademarks of Applied Wave Research, Inc. All other marks are the property of their respective holders.

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