New tutorial discusses diagnosing defects and variances on DDR memory buses and high-speed serial IO

Richardson, TX (Dec 12, 2013) – Slight variances and defects on circuit boards are more difficult than ever to detect and diagnose. Plus, they can result in system crashes and degrade performance later on because their harmful effects are cumulative. A new tutorial by ASSET InterTech ( investigates how advanced test and debug tools based on instruments embedded in chips are able to identify the root causes of defects and variances in complex chips and circuit boards.

“What we’ve seen is that in an era of shrinking chip and board geometries, higher speeds, and greater densities, legacy test technologies no longer provide the access and defect coverage they once did,” said Adam Ley, Chief Technologist, Non-intrusive Board Test and JTAG, for ASSET
InterTech and one of the three authors of the tutorial. “Even the slightest operational variance outside of the board’s specified tolerances could cause problems later when performance degrades or intermittent system crashes occur.”

A Tutorial: Detection and Diagnosis of Printed Circuit Board Defects and Variances” is available
now on the ASSET website at

Other informative eBooks, white papers and videos on issues relating to chip, board and system debug, validation and test can be downloaded from:

About ASSET InterTech

ASSET InterTech is a leading supplier to the electronics industry of tools based on embedded instrumentation. Its ScanWorks platform overcomes the limitations of external test and measurement equipment by applying instrumentation embedded in semiconductors to perform chip and circuit board debug, design validation, manufacturing test and field support. ASSET’s
recent acquisition of Arium, Inc., adds a powerful suite of firmware debug and trace tools to the ScanWorks platform. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.

Follow us on:




You Tube:



Read the complete story ...

Review Article Be the first to review this article
 True Circuits: IOT PLL


Featured Video
Design Verification Engineer for intersil at Morrisville, North Carolina
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Applications Engineer for intersil at Palm Bay, Florida
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise