MEDIA ALERT: Cadence Hosts Front-End Design Summit

SAN JOSE, CA -- (Marketwired) -- Nov 25, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS)

Learn how to achieve faster design closure with physically-aware design knowledge at this year's Front-End Design (FED) Summit. This day-long event will educate attendees on how to save design closure time and boost performance by incorporating knowledge of physically-aware design early into the front-end design implementation flow.

WHEN:
Thursday, December 5, 2013

WHERE:
Cadence Design Systems
Building 10 Auditorium
2655 Seely Ave.
San Jose, CA 95134

MORE ABOUT THE SUMMIT:
FED summit attendees will network with fellow logic designers and speak directly with Cadence® R&D experts about Encounter® RTL Compiler, Encounter Test, and Conformal® applications. At this day-long technical event, attendees will:

  • Hear from design teams about the challenges they faced during logic synthesis, advanced low-power design and verification, engineering change order (ECO), and design-for-test (DFT) implementation, and the strategies they employed to address them
  • Discover how best to achieve power, performance, and area goals on industry-leading IP cores
  • Network, share your knowledge, and exchange best practices with your industry peers

For the full agenda, please click here.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

© 2013 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Conformal, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Add to Digg Bookmark with del.icio.us Add to Newsvine

For more information, please contact:
Cadence Newsroom
408-944-7226

newsroom@cadence.com 





Review Article Be the first to review this article
CST: Webinar November 9, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise