"Until now, there has been no automated way to get a design specified at the algorithm level, from tools such as The MathWorks' Simulink, into high-quality RTL code," said Jeff Garrison, director of marketing, Synplicity. "A common approach was to hand off the RTL generation task to someone other than the DSP algorithm architect, resulting in numerous iterations. This method is error prone and extremely time consuming. With the Synplify DSP software, we're leveraging the widely used floating-point and fixed-point data types from The MathWorks to provide a single representation of the system design in Simulink. The design is implemented from the fixed-point model that has been verified in the Simulink environment. This removes ambiguity that can occur when manually writing RTL."
"DSP designers are increasingly targeting FPGAs for implementation of high-performance DSP designs," said Ken Karnofsky, marketing director for DSP and communications products at The MathWorks. "Synplicity has delivered sophisticated tools for users to generate high-quality RTL code from Simulink that not only delivers impressive QoR, but leverages the comprehensive DSP simulation and analysis already built into Simulink."
Implementing DSP algorithms in hardware can result in an order of magnitude performance increase over standard DSP processors and with the growing demand for enhanced DSP performance for applications such as video/image processing, wireless networking, HDTV, set-top boxes and military and aerospace products, the rate of growth for hardware-based DSPs continues to rise.
System-Level Optimizations and Increased Productivity
The new Synplify DSP software optimizes Simulink-based designs at the system level prior to RTL generation, using algorithms such as system-level re-timing that greatly improves performance of the DSP implementation.
Automatic multi-channelization addresses the time-consuming issue of deciding the optimum number of channels for a particular design. With this patent-pending technique, the designer can perform a quick "what-if" analysis on thread capacity by automatically generating a multi-channel system from a single-channel specification, resulting in a simplified and faster design process.
The new software also uses a unique folding algorithm that allows the user to quickly trade off between performance and area. Because DSP algorithms often consume large numbers of expensive hardware functions such as multipliers, the Synplify DSP tool automatically shares expensive resources within a performance budget. The area/performance trade-off analysis is performed before the implementation process, saving design iterations and large amounts of circuit area.
In addition to generating high-quality RTL code, the Synplify DSP software also produces a test bench that can save designers additional time during the verification process. The generated RTL model can then be verified in any HDL simulator using the stimulus from the Simulink environment. The result is a single-source verification methodology from system model to gates.
Seamless Integration with The MathWorks Simulink Environment
Included in the Synplify DSP software is a set of functional blocks commonly used in DSP design, such as filtering (FIR, IIR), transforms, math functions, CORDIC, signal operations, memories and control logic. These technology-independent blocks are tightly integrated into The MathWorks environment, allowing the algorithm designer to continue to use familiar Simulink capabilities such as discrete-time simulation, multi-rate management, fixed point quantization and scope debugging. With the Synplify DSP toolbox, users can automatically create high-quality RTL code and a test bench from Simulink specification.
Pricing and Availability
Pricing for the Synplify DSP software starts at $29,000 (U.S.) for a one-year, time-based license. Beta software is available now with production expected in June 2004. For more information on the Synplify DSP software, visit Synplicity at http://www.synplicity.com or contact your local Synplicity representative.
Synplicity(R) Inc. (Nasdaq: SYNP) is a leading supplier of innovative synthesis, verification and physical implementation software solutions that enable the rapid and effective design and verification of semiconductors. Synplicity's high-quality, high-performance tools significantly reduce costs and time-to-market for FPGA, Structured/Platform ASIC and cell-based/COT ASIC designers. The company's underlying Behavior Extracting Synthesis Technology(R) (BEST(TM)), which is embedded in its logical, physical and verification tools, and has led to Synplicity's top position in FPGA synthesis, now provides the same fast runtimes and quality of results to ASIC and COT customers. The company's fast, easy-to-use products support industry standard design languages (VHDL and Verilog) and run on popular platforms. Synplicity employs over 270 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, California. For more information visit http://www.synplicity.com.
This press release contains forward-looking statements including, but not limited to, statements regarding the performance and achievements of Synplicity's Synplify DSP software. In some cases, you will be able to identify forward-looking statements by terminology such as "may," "will," "should," "expects," "believes" or the negative of these terms or other comparable terminology. These statements are only predictions and involve known and unknown risks, uncertainties and other factors that may cause the actual achievements or performance of the Synplify DSP software to differ materially from the forward-looking statements, including the performance and quality of our software products relative to other comparable software, latent defects, design flaws or other problems with the Synplify DSP software and the growth and changing technical requirements in the programmable semiconductor market. For additional information and considerations regarding the risks faced by Synplicity, see its annual report on Form 10-K for the year ended December 31, 2003 as filed with the Securities and Exchange Commission, as well as other periodic reports filed with the SEC from time to time, including its quarterly reports on Form 10-Q. Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee the future performance or achievements of its software. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy or completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement.
Synplicity, Synplify and Behavior Extracting Synthesis Technology are registered trademarks of Synplicity Inc. BEST is a trademark of Synplicity Inc. All other names mentioned herein are the trademarks or registered trademarks of their owners.
Synplicity, Inc. Jeff Garrison, 408/215-6000 (Reader) Email Contact or Porter Novelli Steve Gabriel, 408/369-1500 (Press) Email Contact