Real Intent Unveils Major Enhancements in Ascent XV for Early Functional Verification of Digital Designs

SUNNYVALE, Calif. –  Sept. 19, 2013 Real Intent, Inc., a leading provider of EDA software products today announced a new release of its Ascent X-Verification System (XV) tool for early functional analysis of digital designs, adding significant enhancements for initialization analysis, and the detection and management of unknown logic values (Xs). All Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional RTL simulation, leading to both improved quality of results (QoR) and productivity of design teams.

“Analysis and optimization of design initialization in the presence of X’s is a new requirement for SoC sign-off due to modern power-management schemes,” said Graham Bell, vice-president of Marketing at Real Intent.  “Ascent XV provides the necessary analysis of initialization sequences to ensure they are complete and optimal for various power states in an SoC.  It provides the same best-in-class verification performance and debug efficiency as our other Ascent products, uncovering issues prior to digital simulation and synthesis.”

Ascent XV identifies X-sources and potential X-propagation issues early-on in Verilog RTL or netlist designs. It enables the detection and debug of functional issues caused by X-optimism at RTL, prior to synthesis. It also eliminates unnecessary X’s caused by X-pessimism at the netlist. Ascent XV analysis can catch issues prior to RTL sign-off, driving costs down and avoiding monotonous, error-prone debug at the netlist level. Notable features for the new Ascent XV release include:

  • Initialization analysis that reports flops and latches uninitialized after the reset sequence
  • Reset and retention-flop optimization that ensures complete initialization with minimal hardware and routing requirements for savings in area and power
  • Hazard analysis that reports design susceptibility to X-hazards, and automatically detects and reports all X-sources in the design
  • SimPortal that enables Verilog simulation to detect and debug real X-optimism issues, and to model low power retention cells at RTL
  • A debugger that correlates X-optimistic and X-pessimistic signals to X-sources

To see a video interview of Pranav Ashar, CTO at Real Intent, about Ascent XV and the need for X sign-off, please visit:


The latest release of Ascent XV is available immediately for download from the Real Intent web-site.

About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit for more information.

CDC:      Clock Domain Crossing
EDA:      Electronic Design Automation
FSM:      Finite-State Machine
GUI:       Graphical User Interface
IEEE       Institute of Electrical and Electronics Engineers
RTL:       Register Transfer Level
SoC:      Systems-on-Chip

Ascent and Meridian are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.

Press contact:
Sarah Miller for Real Intent
ThinkBold Corporate Communications
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