The new Reference Flows are: 1. TSMC's 16FinFET Digital Reference Flow, providing comprehensive technology support to address post-planar design challenges including extraction, quantized pitch placement, low-vdd operation, electromigration, and power management. 2. The 16FinFET Custom Design Reference Flow, offering full custom transistor-level design and verification including analog, mixed-signal, custom digital and memory. 3. The 3D IC Reference Flow, addressing emerging vertical integration challenges with true 3D stacking.
"These Reference Flows give designers immediate access to TSMC's 16FinFET technology and pave the way to 3D IC Through-Transistor-Stacking (TTS) technology," said TSMC Vice President of R&D, Dr. Cliff Hou. "Delivering our most advanced silicon and manufacturing technologies as early and completely as possible to our customers is a major milestone for TSMC and its OIP design ecosystem partners."
16FinFET Digital Reference Flow
The 16FinFET Digital Reference Flow uses the ARM Cortex™-A15 multicore processor as a validation vehicle for certification. It helps designers adopt the new technology by addressing FinFET structure related challenges of complex 3D Resistance Capacitance (RC) modeling and quantized device width. In addition, the flow provides methodologies for boosting power, performance and area (PPA) in 16nm, including low-voltage operation analysis, high-resistance layer routing optimization for interconnect resistance minimization, Path-Based Analysis and Graph-Based Analysis correlation to improve timing closure in Automatic Place and Route (APR).
16FinFET Custom Design Reference Flow
The 16FinFET Custom Design Reference Flow enables custom design by addressing the growing complexity of 16FinFET process effects and provides methodologies for design compliance in 16nm manufacturing and reliability.
3D IC Reference Flow
The 3D IC process produces significant silicon scaling, power and performance benefits by integrating multiple components on a single device. TSMC's 3D IC Reference Flow addresses emerging integration challenges through 3D stacking. Key features include Through-Transistor-Stacking (TTS) technology; Through Silicon Via (TSV)/microbump and back-side metal routing; and TSV-to-TSV coupling extraction.
About Open Innovation Platform
OIP promotes innovation for the semiconductor design community and ecosystem partners based on TSMC's complete technology portfolio. OIP includes a set of ecosystem interfaces and collaborative components initiated and supported by TSMC that efficiently empower innovation throughout the supply chain, enabling the sharing of newly created revenue and profitability. OIP initiatives include reference flows, third-party IP validation, TSMC library IP, design kits and an online design portal.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry segment's largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company's owned capacity in 2013 is expected to be about 16.5 million (8-inch equivalent) wafers, including capacity from three advanced 12-inch GIGAFAB™ facilities, four eight-inch fabs, one six-inch fab, as well as TSMC's wholly owned subsidiaries, WaferTech and TSMC China. TSMC is the first foundry to provide 28-nanometer production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.
TSMC Spokesperson: Lora Ho, TSMC Senior VP & CFO, Tel: 886-3-505-4602, TSMC Acting Spokesperson: Elizabeth Sun, Director, TSMC Corporate Communication Division, Tel: 886-3-568-2085, Mobile: 886-988-937999, E-Mail: Email Contact