DCD’s D2692 UART IP Core offers more

September 06, 2013 -- The D2692 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681. But on the contrary to it, DCD’s IP Core offers additional features and deeper FIFOs, like 8 character receiver, 8 character transmit FIFOs, watch dog timer for each receiver, mode register 0, extended baud rate, programmable receiver and transmitter interrupts.

The D2692 Dual Universal Asynchronous Receiver/Transmitter is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in just one single package. DCD’s IP Core interfaces directly with microprocessors and may be used in a polled or interrupt driven system, furthermore provides modem and DMA interface. The operating mode and data format of each channel can be programmed independently. - Additionally, each receiver and transmitter can select its operating speed – says Jacek Hanke, DCD’s CEO - as one of 27 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The opportunity to program independently the operating speed of the receiver and transmitter, denotes the UART particularly attractive for dual-speed channel applications like eg clustered terminal systems.

Every receiver is being equipped with fifo to minimize the potential of receiver over-run and to reduce interrupt overhead in interrupt driven systems. Moreover, the D2692 UART IP Core ensures a flow control capability, to disable a remote DUART transmitter, when the receiver buffer is full. To make this design even more functional, there’ve been added multipurpose 7-bit input port and a multipurpose 8-bit output port. They can be used as general purpose I/O ports or can be assigned to specific functions (eg clock inputs or status/interrupt outputs) under program control.

 

More information:

http://dcd.pl/ipcore/785/d2692/



Read the complete story ...


Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs


Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy