Tabula Announces the Availability of Stylus Compiler Version 2.7.2

September software release features 4-port 100G top-of-rack switch reference design

SANTA CLARA, Calif., Sept. 4, 2013 — (PRNewswire) — In a continuing move to help make network infrastructure systems more responsive to applications' dynamic needs, Tabula, Inc., announced today the availability of version 2.7.2 of its Stylus® compiler supporting its ABAX®2 P-Series of devices.  The new capabilities of Stylus compiler include a 100G top-of-rack (ToR) switch reference design targeting next-generation datacenters, along with several new features aimed at further improving user experience.

4-Port 100G Top-of-Rack Switch Reference Design:

This reference design lays the foundation for an Ethernet switch development platform using ABAX2 devices.  With the advance of 100 Gigabit Ethernet (GbE) technology for datacenters, there is a growing demand for silicon systems that support line-rate packet processing. This reference design demonstrates how the Spacetime® architecture combined with the ABAX2 device's rich feature set and capabilities can be applied to these high-performance systems in the domain of 100 GbE packet processing and switching. This reference design consists of a collection of functional blocks which provides a platform for classification, filtering, forwarding and scheduling of packets on networks with 100 GbE interfaces.

More about Stylus compiler

Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers, using industry-standard RTL inputs and design constraints. The suite automatically exploits the unique advantages of Tabula's 3D Spacetime architecture, unleashing the ABAX2 3PLDs' unmatched capabilities and achieving unparalleled performance with surprising ease. The software integrates cutting-edge timing-closure technologies, including sequential timing, router-aware placement, and automatic co-optimization of performance and density.  In addition, to help users take full advantage of the ABAX2 P-Series of device's unmatched embedded RAM capacity and throughput, Stylus compiler transparently infers multi-port memories (up to 24 ports) from RTL, automatically packing small user memories and folding wide user memories into the device's on-chip RAM blocks.

Availability:

Stylus version 2.7.2 is available now

About Tabula:

Tabula is the industry's most innovative programmable logic solutions provider, delivering breakthrough capabilities for today's most challenging systems applications. The company's ABAX2 family of general-purpose 3D programmable logic devices (3PLDs) based on Tabula's patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications, but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees, and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at www.tabula.com

© 2013 Tabula, Inc. All rights reserved. Tabula, the Tabula logo, ABAX, the ABAX logo, Spacetime, the Spacetime logo, Stylus, the Stylus logo and other designated brands included herein are trademarks of Tabula, Inc. in the United States and other countries. All other trademarks are property of their respective owners.

SOURCE Tabula, Inc.

Contact:
Tabula, Inc.
Sabrina Joseph, Managing Partner, Morphoses, (408)236-7373
Email Contact
Web: http://www.tabula.com




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