Toshiba Introduces MIPI® CSI2 Interface Bridge IC Integrating De-Interlacing and Video Scaling Functions

Contributes to Reduce Video Preprocessing Load on Host Processors

TOKYO — (BUSINESS WIRE) — September 3, 2013Toshiba Corporation (TOKYO:6502) today announced that it has launched “T358749XBG”, an interface bridge IC from HDMI® to Mobile Industry Processor Interface (MIPI®) that integrates video de-interlacing and video scaling. Sample is available and mass production is scheduled to start in December this year.

Toshiba's MIPI(R) CSI2 Interface Bridge IC "T358749XBG" (Photo: Business Wire)

Toshiba's MIPI(R) CSI2 Interface Bridge IC "T358749XBG" (Photo: Business Wire)

The new IC’s integrated video preprocessing functions of video de-interlacing, video scaling and video format conversion replace software processing and significantly reduce memory bandwidth and video processing requirements on the host processors deployed in consumer electronics.

The IC supports multiple audio interfaces, including I2S, TDM, S/PDIF, and MIPI® Serial Low-power Inter-chip Media Bus (SLIMbus®), enabling use in a wide range of applications.

Key Features

1. Integrated video de-interlacing, video scaling and video format conversion, contributing to reduce memory bandwidth and video processing requirements on the host processors.

2. HDMI® 1.4 support

- Up to 1080P @ 60fps video format (RGB, YcbCr444: 24-bpp, YcbCr422 24-bpp)
- HDCP 1.3
- 3D support

3. Availability of any of the four audio interfaces: I2S, TDM, SPDIF or SLIMbus®

4. Maximum 1Gbps/lane link speed MIPI® CSI2 interface

5. Maximum 165MHz HDMI clock speed

Applications

A wide range of consumer electronics and industrial applications, such as smart set-top boxes, smart TVs, smart monitors, and small form-factor PCs

 

Main Specifications

Par Number   TC358749XBG
Input Interface

HDMI® 1.4
Clock speed 165MHz (Max)

Output Video Interface MIPI® CSI2 4 Data lanes (Up to 1Gbps/lane)
Output Audio Interface

I2S, TDM, SPDIF or SLIMbus®

Source Voltage

MIPI®/Core/PLL: 1.2V
HDMI®: 3.3V
I/O: 1.8V-3.3V

Package FPGA80 (7mm x 7mm, 0.65mm pitch)
Mass Production Schedule   December, 2013

1 | 2  Next Page »



Review Article Be the first to review this article

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Technical Support Engineer for EDA Careers at Freemont, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy