International Wafer-Level Packaging Conference (IWLPC) Program Finalized and Registration Now Open

Minneapolis, MN - The SMTA and Chip Scale Review magazine are pleased to announce the presentation line-up for the 10th Annual International Wafer-Level Packaging Conference.  The IWLPC will be held November 5-7, 2013 at the DoubleTree by Hilton Hotel in San Jose, California.  Registration is now available on-line and Early Bird conference pricing is in effect until October 4, 2013, after which registration prices will go up $100.

On Tuesday, November 5, 2013, four application-oriented tutorials on Interposers, TSV’s, Wafer-Level Packaging, and Choosing Between Technologies will be instructed by experts in the field including Rao Tummala, Ph.D., from Georgia Institute of Technology, Luu Nguyen, Ph.D., from Texas Instruments, John H. Lau, Ph.D., from the Industrial Technology Research Institute (ITRI), and Herbert J. Neuhaus, Ph.D., TechLead Corporation. 

The conference, on November 6 and 7, includes three tracks of technical paper presentations covering Wafer Level Packaging, 3-D (Stacked) Packaging, and MEMS Packaging.  With a record number of abstracts received this year, the technical committee added two technical sessions on 2.5/3D Integration to help accommodate the many topics.  A special session for Metrology and Test was created to focus on this under-served area of technology. A strong lineup of plenary speakers and panelists from the world of 3D and MEMS was assembled to provide success stories and offer a glimpse of new and emerging technologies and applications.

Paul Wesling, a CPMT Society Distinguished Lecturer, is scheduled to give an exciting and colorful history of device technology development and innovation in his presentation "The Origins of Silicon Valley: Why and How It Happened Here” during the Keynote Breakfast on November 6.

The exhibition expanded to include over 50 solutions providers showcasing everything from materials to equipment, from market research to metrology, from foundries to OSATs. Though mostly sold out, a few booths still remain in the exhibition.

Visit http://www.iwlpc.com for more information. 

The SMTA membership is an international network of professionals who build skills, share practical experience and develop solutions in electronic assembly technologies, including microsystems, emerging technologies, and related business operations.

Chip Scale Review, now entering its 16th year, is the leading international magazine serving the semiconductor, IC and electronic device packaging market.



Contact:

Patti Hvidhyld
952-920-7682
Email Contact




Review Article Be the first to review this article
CST: Webinar November 9, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise