Real Intent Joins Synopsys in-Sync Program

SUNNYVALE, Calif. – July 8, 2013 Real Intent, Inc., a leading provider of EDA advanced sign-off verification solutions, today announced it has joined the Synopsys in-Sync™ program for two of its flows – the Synopsys VCS® Verilog simulator tie-in to Real Intent’s Ascent™ and Meridian™ products; and the Synopsys HDL Compiler™ tool flow tie-in to its Meridian products.

“Since our beginning, Synopsys has advanced tool interoperability via standards organizations and our own programs including in-Sync,” said Karen Bartleson, senior director of Community Marketing at Synopsys, Inc. “By joining in-Sync, Real Intent can work with us in verification and synthesis to help our mutual customers meet their stringent design flow requirements."

CDC analysis and verification are vital at both the pre- and post-synthesis stages of design to ensure against signal metastability. Correct and complete CDC analysis and verification require a clean and correct SDC file that is also used in the synthesis, and timing analysis steps. The Meridian flow with HDL Compiler ensures compatibility for SDC files.  The tie-in of VCS to Ascent and Meridian products provides dynamic verification of both X-propagation and metastability issues.

Graham Bell, vice president of Marketing at Real Intent said, “Our solutions play well with others in the industry, and we are especially pleased to become a member of Synopsys’ in-Sync Program. Our membership provides access to Synopsys’ market-leading verification and synthesis technologies to ensure interoperability, and brings time and cost efficiencies to our mutual customers who now can take advantage of a proven and qualified design flow.”

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit for more information.

ASIC:     Application-Specific Integrated Circuit
CDC:      Clock Domain Crossing
EDA:      Electronic Design Automation
FPGA:     Field-Programmable Gate Array
HDL:       Hardware Description Language
RTL:        Register Transfer Level
SDC:       Synopsys Design Constraints
SoC:       Systems-on-Chip

Ascent and Meridian are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.

Press contact:
Sarah Miller for Real Intent
ThinkBold Corporate Communications
Email Contact

Review Article Be the first to review this article


Featured Video
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Upcoming Events
SEMICON Europe at Grenoble France - Oct 25 - 27, 2016
ARM TechCon 2016 at Santa Clara Convention Center Santa Clara CA - Oct 25 - 27, 2016
Call For Proposals Now Open! at Santa Clara Convention Center, Santa Clara, CA California CA - Oct 25 - 27, 2016
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy