Real Intent to Exhibit at CDNLive EMEA 2013 in Munich, May 7 & 8

SUNNYVALE, CALIF. – May 1, 2013 –  


Real Intent, whose advanced verification solutions accelerate electronic design sign-off, eliminate complex failures in SoCs, and lead the market in performance, capacity, accuracy and completeness


Will exhibit its two product families – Ascent products for early functional verification prior to synthesis, and Meridian products for advanced sign-off verification not possible with simulation or static timing analysis – at the Designer Expo at CDNLive EMEA, the Cadence User Conference in Munich, Germany, next week.

  • Ascent Lint is the industry’s fastest and lowest-noise RTL lint solution. Its smart rules perform syntax and semantic checks for today’s complex SoC designs. Ascent Lint is unique in the industry in terms of delivering high capacity, comprehensiveness and ease of debug.
  • Ascent Implied Intent Verification (IIV) is an early functional verification tool that automatically finds elusive bugs in RTL. It performs comprehensive verification using automatic check formulation followed by deep-sequential formal analysis, detecting up to 50-percent of design functional errors prior to testbench development and simulation.
  • Ascent X-Verification System (XV) detects and isolates X-propagation issues early, in Verilog RTL, eliminating the masking of functional bugs (X-optimism) and the appearance of unnecessary X’s (X-pessimism) prior to synthesis. It stops hidden functional bugs from slipping through to silicon.
  • Meridian CDC, the fastest, highest-capacity and most precise CDC solution in the market. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC or FPGA devices are received reliably. With a capacity exceeding 100M gates, Meridian CDC is the only solution that enables all aspects of CDC sign-off.
  • Meridian Constraints is a comprehensive constraint management solution. It offers high-performance constraint validation, template generation, coverage analysis, equivalence checking and timing exception verification.

CDNLive EMEA brings together Cadence® technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs and systems.


Tuesday, May 7 and Wednesday, May 8, 2013 during all breaks and meals
Dolce Hotel, Expo Area
Andreas-Danzer-Weg 1,
85716 Unterschleißheim,

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit for more information.


ASIC:     Application-Specific Integrated Circuit
CDC:      Clock Domain Crossing
EDA:      Electronic Design Automation
FPGA:     Field-Programmable Gate Array
RTL:       Register Transfer Level
SoC:      Systems-on-Chip

Meridian and Ascent are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.

Press contact:
Sarah Miller for Real Intent
ThinkBold Corporate Communications
Email Contact

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