Concurrent validation methodology delivers first-time silicon success
SANTA CLARA, Calif. — (BUSINESS WIRE) — April 30, 2013 — Invarian, Inc., a premier provider of full-chip concurrent sign-off analysis solutions for complex integrated circuit (IC) designs, has developed advanced algorithms that enable fast and accurate full-chip analysis for large capacity designs. The company’s R&D team takes a holistic approach for tackling analog and digital designs with concurrent analysis of power, signal timing, electromigration, voltage, temperature, and die/packaging parameters.
Previous generation physical design tools have not kept pace with today’s designs. Inaccurate and inconsistent results lead to expensive re-spins; it is not uncommon for post-production numbers to deviate from simulation results by up to 20%, leading to excessive margins. Verification takes too long and overall sign-off turnaround time is unacceptable. Designs are often too large or too complex to handle efficiently. Simulation capacity is limited to a few clock cycles. The proliferation of point tools involved in sign-off analysis provides a fragmented picture and can often lead to ambiguous results. Stand-alone tools are hard to integrate into an existing flow and the workarounds can induce errors that are difficult to isolate.
Invarian believes that accurate IC signoff results cannot be achieved without concurrent analysis of all parameters affecting IC behavior. Without concurrent analysis, lack of correlation between simulated and real-life IC behavior causes severe tape-out problems. Invarian technology detects problems that are usually only detected after manufacturing; sign-off results correlate with real physical measurements within two percent. Massive parallelization delivers fast runtimes and innovative algorithms allow all engines (power, thermal, etc.) to run in a single, fast-converging, iterative process. The solutions scale with process node, design size and complexity, with a simulation capacity of thousands of clock cycles.
Invarian technology can be used as early in the design flow as the placement stage. Easy integration into existing flows is assured by adherence to industry standards and the use of a powerful GUI and “what-if” capabilities. As well as being complementary to major EDA design flows, Invarian solutions support all leading foundry process nodes.
“Accuracy is key for sign-off analysis,” said Alex Samoylov, COO, vice president of engineering and co-founder of Invarian. “The methodology we have devised does not use predefined corners for analysis. Sign-off analysis is performed in the simulation environment that represents real-life conditions. And we have the only tools on the market that implement concurrent analysis of parameters affecting the accuracy of sign-off data.”
One of Invarian’s major advantages compared to existing solutions is the new methodology created by the company’s R&D team in Moscow and Silicon Valley. To deal with all behavioral parameters at once requires much better modeling correlation at all stages of design and development. Led by Samoylov, the R&D team located in Moscow has applied their deep knowledge in physics and mathematics, as well as extensive EDA software experience, to create a suite of products built from the ground up for accurate concurrent analysis.
Some of the changes in methodology that enable Invarian to deliver correct-by-design sign-off analysis include:
- Time domain analysis that scales with design size.
- A focus on accuracy and efficiency across the flow.
- Efficient use of parallel architecture to significantly shorten design runs.
- Use of the latest multi-core processing methodology not available to traditional tools.
- Concurrent analysis of power-voltage-thermal.
- Integration and ease of use across the design flow.
- True 3D thermal analysis that goes beyond the chip to encompass the package and the environment.
- Easy control of 3D thermal issues.
“Fast adaptation of Invarian’s revolutionizing solutions at some of the world’s leading processor, switch and mobile companies underlines how well Invarian’s tools are designed for engineers who require fast, accurate results from gate level through to the 3D package environment,” said Invarian CEO Jens Andersen. “The strength of our combined experience and the proven expertise of the R&D team and executives helps our customers to achieve results that correlate with physical reality and is the best bet for first time silicon success increasing overall ROI.”
Invarian will be demonstrating their full-chip concurrent sign-off analysis solutions at the Design Automation Conference (DAC) in Austin, Texas, from June 3-5 in booth #1332. Contact Invarian at www.Invarian.com to set up a suite appointment.
is revolutionizing full-chip sign-off analysis for complex,
high-performance integrated circuits (ICs). The team of founders and
engineers at the R&D headquarters in Moscow has developed a new
methodology using parallel architecture and concurrent
power-voltage-thermal analysis to provide engineers with fast, accurate,
consistent results from gate level through the 3D package environment.
Invarian sign-off analysis for analog, digital and mixed-signal ICs
identifies post-manufacturing failures before tape-out, reducing costly
re-spins. Customers are using this cost-effective, comprehensive
to develop digital and analog/mixed-signal chips in areas such as mobile
technology, CPUs, wireless and networking, for a variety of processes
including below 20nm. For more information visit