Algo-Logic Systems Launches 2nd Generation Ternary Search Engine (TSE2) Solutions for the new Tabula ABAX2 P-Series of 3PLD.

Companies successfully collaborate to deliver industry-best programmable algorithmic search solutions enabling 150 MSPS at 100 Gbps line rate.

Santa Clara, California, March 27, 2013 -- Algo-Logic Systems, Inc., a recognized leader in providing hardware-accelerated, real-time, deterministic, ultra-low-latency packet processing, accelerated finance, and embedded systems, announces the launch of their second-generation Ternary Search Engine (TSE2) capable of running on Tabula’s new ABAX2 P-series of 3D Programmable Logic Devices (3PLDs).

The TSE2 search engine running on the ABAX2P1 device performs high-speed packet classification for customized search of Ethernet, IPv4 and IPv6 packets. The TSE2 implements the search component of Access Control Lists (ACL) for use in firewalls, routers, flow controllers, VOIP management systems, L2 to L7 content matching engines, load balancers and Software-Defined Networks (SDN).

The high performance ultra-fast TSE2 search engine matches header and payload data at 100 Gbps line rates with deterministic, low latency. The highly customizable TSE2 search engine performs searches at five-times the speed of TSE1. Key performance metrics for the TSE2 are:

  • 150 million searches per second (MSPS) per core, scalable to 600 MSPS with 4 cores per device.
  • Large key-size widths of up to 640 bits (suitable for high N-tuple matching in OpenFlow)
  • Comparable to legacy CAM capacity of 120 Mb (on-chip) to 7.6 Gb (with off-chip DDR3)
  • Table sizes ranging from 512 fully associative to 12M entries of exact flow match with DDR3
  • Table Lookup low-latency of 256 ns on-chip and 450 ns with hybrid (on-chip memory + DDR3)

“The combination of the ABAX2P1 device’s breakthrough memory and logic capabilities, and Algo-Logic System’s expertise in developing deterministic packet processing and search engine solutions result in search engine performance levels previously unattainable in a programmable chip” said Dennis Segers, Tabula’s Chief Executive Officer.

"We are excited to partner with Tabula to launch the industry-best TSE2 search engine core on Tabula’s newly announced ABAX2P1 device using Intel’s advanced 22nm Tri-gate process technology. The high performance and low latency TSE2 search engine cores gateware-accelerate packet classification and search capabilities of datacenters, cloud service providers, software-defined networking (SDN), storage systems and network appliances.” said John Lockwood CEO of Algo-Logic Systems, Inc.

Each Algo-Logic second-generation TSE2 core performs 150 million searches per second (MSPS) enabling wire-speed, 100 Gbps packet processing. Moreover, by instantiating four cores, our customers can search 600 MSPS to support up to 400 Gbps of traffic using a single programmable logic device. Consequently, the 2nd generation TSE search engine technology increases by orders of magnitude the throughput of traffic that can be processed by Internet Service Providers (ISPs), Hosting Service Providers (HSPs), and operators of Software-Defined Networks (SDNs) including OpenFlow, datacenters, big-data processing systems, accelerated finance systems, network security devices, VOIP switches, firewalls, routers, and virtualized cloud computing systems.

About Algo-Logic Systems:

Algo-Logic Systems is a recognized leader and developer of fast time-to-market gateware libraries forField Programmable Gate Array (FPGA) devices used in packet processing in datacenters, mobile embedded hardware systems and accelerated finance. In addition, it also has extensive experience building routers, data center switches and customized network processing system solutions in FPGA/ASIC/SoC logic.

About Tabula:

Tabula is the industry’s most innovative programmable logic solutions provider, delivering breakthrough capabilities for today’s most challenging systems applications. The company’s ABAX² P-series family of general-purpose 3D programmable logic devices (3PLDs), based on Tabula’s patented Spacetime architecture and supported by its Stylus software, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. 


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