Calypto Participates in Technical Session at DATE 2013: Detecting Isomorphisms in Logic Design

SAN JOSE, Calif. — (BUSINESS WIRE) — March 14, 2013 — At DATE 2013, Calypto® Design Systems, Inc., the leader in electronic system level (ESL) hardware design and register transfer level (RTL) power optimization, will present in a technical session on an innovative approach to detecting isomorphisms in logic design and formal verification. This work is based on collaboration between Calypto and UC Berkeley that is aimed at simplifying formal analysis of circuit logic. Calypto technologies let designers create high-quality, low power ASIC and FPGA hardware products. Calypto’s three product families (PowerPro®, Catapult® and SLEC®) offer customers solutions ranging from RTL power reduction to C++/ SystemC high-level synthesis.

WHAT:

 

Technical Session 649: A Semi-Canonical Form for Sequential AIGS

 

SPEAKERS:

Alan Mishchenko, Niklas Een and Robert Brayton - University of California, Berkeley, US

Michael Case, Pankaj Chauhan and Nikhil Sharma - Calypto Design Systems

 

WHERE:

Alpexpo Espace Alpes Congres

Grenoble, France
 

WHEN:

Wednesday, March 20, 2013

1430 - 1600

Room, Belle-Etoile

1 | 2  Next Page »



Review Article Be the first to review this article

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Staff Software Engineer - (170059) for brocade at San Jose, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Technical Support Engineer for EDA Careers at Freemont, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy