Discussing prevalence of asynchronous-clock-domain interface errors in mainstream SoC design and solutions to address it
SAN JOSE, Calif. – Nov. 6, 2012 – Real Intent, Inc., at the 2012 IEEE/ACM Workshop on CAD for Multi-Synchronous and Asynchronous Circuits and Systems (MSCAS) – a forum to discuss current challenges of asynchronous design.
Will speak on: “ Async in the Mainstream, More Prevalent Than You Might Think,” in the Clock Domain Crossing session. With the asynchronous paradigm very much a part of mainstream design – and a key issue for designing and manufacturing the typical SOC today – Dr. Ashar will discuss the problem of increased field failures caused by asynchronous-clock-domain interface errors, and solutions being developed to address it.
Thursday, Nov. 8, 2012, 10:55-11:20 a.m., Market 1 & 2, Hilton San Jose, 300 Almaden Blvd., San Jose, CA 95110.
For details on this one day workshop, visit: http://iccad.com/2012_event_details?id=149-4-W
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
Sarah Miller for Real Intent
ThinkBold Corporate Communications