Patents Filed for Five Key Algorithms Used in Advance Debugging of UVM Designs
Milpitas, California, August 8, 2012 – Strengthening its leadership position in SystemVerilog based verification, Axiom Design Automation, provider of fastest path to verification closure for semiconductor design, today announced that it has filed patent applications in five key areas for debugging of UVM technology.
The five patent applications filed include:
- METHOD AND APPARATUS for automatically creating and displaying the testbench hierarchy for UVM based testbenches.
- METHOD AND APPARATUS for automatically creating and displaying the port connectivity schematic for UVM based testbenches.
- METHOD AND APPARATUS for tracing values in design through the use of biometric markers.
- METHOD AND APPARATUS for Synchronization of UVM test bench and design under debug using transactions AUTOMATICALLY extracted from the Simulation Log file without any instrumentation and intervention by the user.
- METHOD AND APPARATUS tracing drivers and value changes on dynamic testbench variables.
“Axiom has always taken pride in being the technology leader in functional verification” said Atiq Raza, Chairman of the Board, Axiom Design Automation. “DesignerUVM incorporates some of the most advanced simulation and debug technology ever developed and the successful filing of the five patents is a testimony to the depth of the research and development activity at Axiom. The new ideas and algorithms we developed are so unique and significant that we have chosen to reveal them, even while protecting them, for the benefit of the industry”.
First showcased to the public at the Design Automation Conference in San Francisco in June, DesignerUVM, incorporating the patent pending technology is in production and customers are already benefiting from the advanced technology.
“While the industry standard UVM is great for the industry, it introduces significant challenges for debugging", stated GarySmith, chief analyst at Gary Smith EDA.” With the maturing of SystemVerilog, debugging is a big competitive differentiator for simulators, as validated by the recent acquisition of SpringSoft by Synopsys. Axiom’s patent filing and customer response proves that Axiom has taken a lead when it comes to advanced integrated debugging environment for UVM testbenches”.
Axiom’s MPSim is industry’s price/performance leading SystemVerilog verification platform. MPSim offers significant new capabilities in simulation performance, debugging, coverage analysis and SystemVerilog enhancements including the newly released DesignerUVM and complete support for VMM, OVM and UVM. Combined with multi-core support, compiled testbench including SystemVerilog and OpenVera, comprehensive coverage closure technology and best-in-class integrated graphical debugger, MPSim offers the most complete verification solution in a single unified kernel architecture for maximum performance.
Axiom Design Automation is a company focused on providing the best-in-class verification platform to address the growing complexity of today’s FPGAs, ICs, SOCs and systems. Axiom’s flagship product, MPSim is the state-of-the-art, industry proven high performance SystemVerilog simulator integrated with an advanced debugger, compiled testbench automation, multiple clock domain verification and comprehensive coverage analysis for quick verification closure. MPSim incorporates SystemVerilog and OpenVera testbench automation with SVA and coverage analysis in single kernel architecture for maximum performance. MPSim is fully compliant with industry standards such as VMM, OVM, UVM, UPF, etc. For more information please visit www . axiom - da . com.
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