Grenoble, France — June 20, 2012 — Tiempo, expert in the design of advanced secured chips, today announced it has proven on silicon its secured transaction platform, TESIC, manufactured on TSMC 130 nm LP process.
As already observed with Tiempo previous clockless circuits, all chip samples were fully functional and matching the expected performance. This successful circuit is another first-time-right design made with Tiempo unique ACC synthesis tool.
Tiempo TESIC is a complete secure platform for the design of integrated circuits implementing secured transactions such as smartcard chips for banking and ticketing, chips for ePassports or NFC secure elements. The TESIC secure platform leverages Tiempo's unique power/performance auto-scaling and tamper-resistant asynchronous technology delivering unprecedented benefits for demanding embedded security applications.
The prototype chips enable Tiempo to confirm the high performances of the TESIC platform for contactless applications. "This is a very important milestone", says Serge Maginot, CEO of Tiempo. "Our clockless design flow having a proven maturity and our TESIC platform being silicon-proven, we are now able to offer a complete chip solution with unmatched performance for secured contactless payment applications."
Tiempo offers unique chip solutions and platforms that target secured transactions and have unmatched hardware security and speed/power performance. Its products are ideal for contactless transactions such as banking, ticketing and NFC as well as ultra-secure circuits. Tiempo solution relies on an innovative and patented clockless design technology using standard hardware description languages and ACC, its unique automated synthesis tool for clockless and delay-insensitive designs. Tiempo is headquartered near Grenoble, France, with US offices in California. More information can be found at www.tiempo-ic.com