This is the May 07, 2012 article for the EDACafe.com EDA Commentary. The article is entitled, “Morning at the Oasys.”
About six months into 2011, having been the EDACafe.com author of both the quarterly EDA Commentary for 8 years and the monthly EDA WEEKLY for some 19 months, and having done in-depth profiles of many EDA, IP and MCAD/MCAE vendors in previous articles, your writer decided to begin the process of scheduling an interview with Rajeev Madhavan, then the colorful CHAIRMAN of MAGMA Design Automation. Our preparatory interactions went as far as obtaining from Rajeev his answers to our starter BIO Questionnaire as well as scoring a series of candid photographs of the MAGMA Chairman in action.
During the summer and early autumn of 2011, dates for the actual interview with Rajeev were repeatedly set, only to be delayed by schedule conflicts on the parts of one or both parties.
Next came the surprise announcement in late 2011 that Synopsys planned to acquire MAGMA. This is when your writer set aside further pursuit of the Madhavan interview idea, in favor of a kind offer from one Nanette Collins  to stay close to the evolving Synopsys-MAGMA story and perhaps eventually resurrect the opportunity for an EDA WEEKLY MAGMA-related article.
Exit MAGMA, Hello Oasys
Alas, once the acquisition of MAGMA was finally consummated in February 2012, and MAGMA disappeared into Synopsys, so did our Rajeev Madhavan story interest .
But that merger also meant that there remained fewer EDA companies in the marketplace offering synthesis technology for teams designing SoCs. That is, just Synopsys and Cadence seemed to remain in the minds of many folks (for synthesis).
“Ah, let’s not forget that private company that our friend Joe Costello  is now affiliated with,” said your writer, referring of course to the still private company based in Silicon Valley, Oasys Design Systems.
At that point in the discussion, Nanette revealed that she had been involved in some Public Relations work for Oasys and that she knew Paul van Besouw, the founder and CEO of Oasys. Busy with several other pressing tasks, the writer asked Nanette to follow up with Oasys.
Shortly thereafter, Nanette booked an appointment with Paul van Besouw and took a trip over to San Tomas Expressway and 101 in Santa Clara, in many people’s minds the geographic epicenter of Silicon Valley. Nanette subsequently offered an interview record of her first meeting with Oasys on behalf of the EDA WEEKLY .
Somewhat later a second interview occurred. The two interviews were recently combined and the result is given below .
The Combined Interview with Oasys
Paul, please tell us about your background.
“I was born and reared in the Netherlands. I am one of the founders of Oasys, along with Johnson Limqueco, vice president of R&D, and Harm Arts, who is also from the Netherlands as it happens. Harm is our CTO .
We were all part of the original R&D team at Ambit Design Systems that was acquired by Cadence over a decade ago. At Cadence, the team focused on physical synthesis, connecting traditional synthesis to physical design.
I have a Master of Science degree in Electrical and Computer Engineering from the Eindhoven University of Technology in The Netherlands. My start in the EDA industry goes back to when I was at the university. I was part of a group doing EDA research. Rajeev Madhavan, who was then starting Ambit, emailed me that he needed software developers who had experience developing RTL synthesis front-ends. I was just finishing my master’s degree, so the timing was perfect. That was 1995. I talked to Rajeev and he invited me to visit to California. I packed my bags and came over, and that is how the whole thing started. It was initially meant to be a six-month assignment and it’s now over 15 years.
Just coming out of university with no industrial experience, it was a great opportunity. We had to build everything from scratch. With a core team of only six people, we built the foundation of the Ambit technology.
You were at Cadence and you decided to quit and start Oasys? What motivated that?
By building synthesis technology at Ambit and separately building physical technology at Cadence, we realized that we had created a suboptimal solution, and then were forcing design teams to deal with it. It is really hard to integrate two separate products, a synthesis product and a place and route product into one and get the best design results. We knew there had to be a better way.
All synthesis tools before Oasys’ RealTime Designer basically went naively from RTL to gates and then threw the gates into optimizers with some level of physical knowledge. But the initial netlist was often so far from what was needed, that it took an incredible amount of time to get close to closing timing.
In traditional synthesis tools, the “integration” was being done at the gate level. This level of integration really didn’t address the fundamental problem –– the fact that the choices you made during RTL synthesis determine the quality of results after place and route.
Since there was no physical information during RTL synthesis, there really wasn’t a way to make the right choice. That triggered a question about how it should really be done –– can you build a tool that produces better quality if you combine RTL synthesis and physical synthesis in a single engine? The answer was not obvious, but we concluded that there should be.
We started Oasys, and tried to figure out how to go from RTL to placed gates in a way where there is much better conversion to physical design. It took the team two years to build a new technology from scratch. The first prototype solution was qualified on an actual customer design. The designers reactions were priceless. After they verified the design and validated the quality of results on site, the design team leader said: “Wow! The run really did take less than 15 minutes!”
Traditional synthesis turns RTL code into a quick-and-dirty netlist and then runs a powerful but slow optimizer on that netlist. OASYS’ goal is to produce the best starting point for physical implementation by producing placed netlists that in turn enable the place and route tool to deliver the targeted quality of results. We put a lot of effort up front to intelligently turn RTL code directly into placed gates, or what we call Chip Synthesis technology. When the timing doesn’t close, we don’t optimize the gates, we go back to the RTL level and re-synthesize, repartition and re-place part of the design.
Last year, we added
DFT capabilities to RealTime Designer, for designers to create a better DFT architecture and chip partitioning. Full-chip DFT synthesis can be performed in a single pass with fast turnaround and without the need for complex DFT abstraction and bottom-up flows.