Xilinx Unveils the Vivado Design Suite for the Next Decade of 'All Programmable' Devices

– Gordan Galic, Technical Marketing Manager

A2e Technologies, Certified Xilinx Alliance Program Member
"Integrating A2e Technologies' H.264 Codecs will be greatly simplified through the Vivado IP Integrator. Implementing H.264 video compression and decompression from 720p to 4K resolutions has been somewhat complicated in the past. Now with the Vivado IP Integrator, designers can perform this integration at the interface level rather than the signal level using a single IP interface standard, AMBA AXI4, with design rule checks that minimize errors. This will make our IP even easier to Plug-and-Play in Xilinx designs."

– Allen Vexler, CTO

Aliathon, Ltd., Certified Xilinx Alliance Program Member
"As a leading provider of FPGA solutions for the OTN market, fast and efficient designs are crucial to Aliathon's success, especially at 100G and beyond. The Vivado Design Suite has helped us minimize chip resources, as well as place and route times. The resulting improvement in power, performance and design iterations allow Aliathon to deliver even better solutions to our customers."

– Steve McDonald, Director 

Hardent Inc., Certified Xilinx Alliance Program Member
"Providing electronic design services to companies with complex requirements, Hardent is pleased with the accelerated productivity introduced by the Vivado Design Suite. We typically push both the clock rate and utilization limits of Xilinx devices, and with its new place and route engine and incremental design flows, Vivado tools will help our mutual customers with demanding designs; such as for the new 2-million-logic cell Virtex-7 2000T FPGA." 

– Simon Robin, President

Missing Link Electronics, Certified Xilinx Alliance Program Member
"Missing Link Electronics develops embedded systems where software and hardware can be configured for the target application. Short turn-around time and predictable synthesis results are very important for delivering such heterogeneous multi-core system FPGA designs. To us, Xilinx's Vivado Design Suite manifests Xilinx's strong commitment to supporting our industry to deliver better embedded systems, faster!"

– Endric Schubert, CTO

Oki Information Systems Co., Certified Xilinx Alliance Program Member
"As a Vivado Design Suite Early Access participant, we used Vivado tools to compile our PCIe DMA Controller (iDMAC) IP, and we've migrated the IP from the ISE Design Suite to the Vivado suite without any problem. Thanks to the intuitive Vivado GUI built on PlanAhead, our engineers are able to learn the Vivado IDE easily and quickly. The adoption of ASIC friendly Tcl scripts further improves the ease of use for our IP design engineers who have prior ASIC design experience. Going forward, we plan to use Vivado tools for large designs and we expect to see significant productivity improvement due to numerous technology breakthroughs, such as high performance synthesis, analytic place and route, and low memory consumption."

– Yasuo Yamamoto, IP Platform Business Unit Leader

OmniTek Ltd., Certified Xilinx Alliance Program Member
"We took part in the partner training for the Vivado Design Suite and were most impressed. We regard the adoption of industry standards such as IP-XACT, SDC and AMBA AXI4 as essential for the proliferation of FPGA IP needed for the largest 28nm devices. The Vivado IP Integrator and IP Packager tools further reduce the design time required for IP development and integration."

– Roger Fawcett, Managing Director

4DSP, Inc., Xilinx Alliance Program Member
"The Vivado Design Suite bridges the gap between flexibility and performance. The ease of creating projects combines smoothly with a straight forward design flow and helps us meet our design requirements fast and efficiently. The generic nature of the AMBA AXI4 interface makes it especially simple to port our existing IP and reference designs to the new 7 series."

– Justin Braun, FPGA Design Manager

Blue Pearl Software, Inc., Xilinx Alliance Program Member
"Our Blue Pearl Software Suite works seamlessly with the Xilinx Vivado Design Suite running on Windows platforms. Our solution for RTL analysis includes linting, clock domain crossing (CDC) and automatic Synopsys Design Constraint (SDC) generation. With our SDCs, we automate the synthesis and place and route phases of FPGA design implementation. Our customers say our software reduces iterations and overall design time, and our Visual Verification Environment ™ makes it easy to use for any level of FPGA designers."

– Shakeel Jeeawoody, Director of Product Marketing

CAST, Inc., Xilinx Alliance Program Member
"The AMBA AXI4 standard interconnect and IP-XACT packaging standard are big advancements in our ongoing goals to make CAST cores easier to integrate and to improve the overall IP experience for CAST customers. The new Vivado Design Suite with its integrated database, better scripting control, and other productivity aids will significantly reduce the time we spend delivering these benefits, especially when multiplied over the fifty-some Xilinx cores we provide."

– Nick Sgoupis, Senior Principal Engineer

Great River Technology, Inc., Xilinx Alliance Program Member
"We see great value in the capability of the Vivado IP Packager to allow us to easily add our ARINC 818 IP to the Vivado Extensible IP catalog. We appreciate that companies who purchase our IP libraries for mission critical, high performance digital video now have a way to deploy the IP throughout their organization with consistency and ease of use."

– Mukul Gadde, Design Engineer

IntoPix s.a., Xilinx Alliance Program Member
"The increased performance delivered by the Vivado Design Suite enabled us to validate recurring upgrades of our IP cores much faster across the full range of Xilinx products. Thanks to the decreased runtime provided by the Vivado tools, we are capable of running multiple implementations of the same IP flavor simultaneously, and validate any slight update to any IP-core."

Katty Van Mele, Director of Business Development

National Instruments Corp., Xilinx Alliance Program Member
"We are excited about the new Vivado Design Suite functionality. The Tcl interface gives us the capability to query the design and generate custom reports. The Xilinx Design Constraint support improves static timing analysis with enhanced support for source-synchronous interfaces. We are also happy to see significantly reduced compile time for our initial designs."

– Omid Sojoodi,  Director of LabVIEW FPGA and Real-Time 

PLDA, Xilinx Alliance Program Member
"PLDA is an industry leader in PCI, USB and TCP/IP IP for FPGAs and we have a broad customer base. We see great value in the capability of the Vivado IP Packager to easily add our popular IP to the Vivado Extensible IP catalog, making it even easier for Xilinx users to access our products. Companies who purchase our IP now have another way to deploy it throughout their organization with a consistency that will accelerate the customer's design productivity and product quality."

– Stephane Hauradou, CTO

Synopsys, Inc., Xilinx Alliance Program Member
"We have worked closely with Xilinx to optimize our Synplify® synthesis products for use with the Vivado Design Suite. With the combination of Vivado tools and Synplify Premier, designers implementing FPGAs and FPGA-based prototypes will be able to realize the benefits of a complete and productive FPGA design flow that delivers the highest quality of results for performance with significantly faster turnaround time."

– John Koeter, Vice President of Marketing for IP

Atrenta, Inc., Xilinx Alliance Program Member
"As the industry looks more toward FPGAs for production designs, Atrenta's collaboration with Xilinx is a great opportunity to focus on interoperability between SpyGlass and the Vivado Design Suite and drive a methodology for FPGA designers. In leveraging Atrenta's SpyGlass platform – the recognized industry leader in RTL linting, clock domain crossing (CDC) and timing constraints for ASIC designs, the new Vivado Design Suite will offer customers targeting Xilinx's industry-leading FPGA devices the same productivity benefits of 'SpyGlass Clean' RTL that ASIC designers have come to expect from Atrenta."

– Piyush Sancheti, Sr. Director, Business Development

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