SOCFIT 3 optimizes soft error mitigation with RTL and derating analysis
ANAHEIM, Calif. — (BUSINESS WIRE) — April 16, 2012 — IRPS Conference--IROC Technologies®, developers of the industry standard for integrated circuit (IC) soft error analysis and prevention, will introduce SOCFIT® 3 at the IEEE International Reliability Physics Symposium (IRPS 2012) in Anaheim, CA from April 15th to 19th. The 3 solution focuses, at circuit level, on assessing the overall failure-in-time (FIT) rate of large integrated circuits (ICs) early in the design phase and produces a list of major contributing elements on the impact of soft errors on performance, especially at 65nm and below. The SOCFIT tool platform is a prediction and analysis tool that links raw cell soft error rate (SER) to circuit SER and system SER.
Soft errors are caused by interactions of natural radiation with silicon that can happen at any time and at any location during the operational life of a device. The smaller the technology, the higher the sensitivity of designs to soft errors, which cannot be eliminated using classic post-manufacturing reliability techniques like burn-in or stress test. Memory is very sensitive to soft errors and, at 65nm and beyond, logic is increasingly at risk. SOCFIT 3 allows chip architects to assess the FIT rate early in the design (RTL, gate netlist), budget mitigation to reach the FIT goal, analyze quickly the effects of derating or masking, optimize the mitigation, and report the FIT rate to their customers with solid technical explanations.
IROC has been in the soft error business for a decade, developing simulation expertise and tools while also providing test and analysis services. Users of SOCFIT 3 can build a database of FIT rate for each individual cell used in a circuit with IROC’s cell level SER assessment tool, TFIT®.
Unlike existing soft error solutions, SOCFIT 3 reports specifically on SER performances and derating factors for chip architects. Its algorithms are specialized for this purpose. Input to the tool are the RTL or gate netlist definition of the chip, timing files, application that runs on the chip and the intrinsic FIT rates of cells in the design library, values provided by the complementary TFIT tool and/or by partner foundries and radiation test. In addition, SOCFIT 3 accelerates the methodology of fault injection in a unique multi-step approach to reduce the overall simulation time, especially for very large designs.
Use of a combination of static analysis and golden simulation to optimize the fault injection campaign makes SOCFIT much faster and more relevant than random Monte Carlo fault injection. Use of proprietary algorithms also contributes to the very fast analyses. User’s benefits stem from the ability to propose mitigation solutions and quickly re-analyze the impact on the whole circuit.
“SOCFIT is a comprehensive tool which solves the complexity of analyzing reliability issues on very large SoC designs. The complexity of the problem is that many sources of errors can affect chip reliability. SOCFIT helps quantify these issues and points to the areas of the design that need to be improved. The tool is helpful to explain the reliability performances of our design to our customer in a clear and quantitative way. IRoC experts have been very helpful and flexible in the deployment of this tool within LSI,” said Miguel Vilchis, reliability engineer and soft error expert at LSI.
“The demand for soft error analysis has been growing since 65nm; designers need to be proactive in assessing and correcting the problem as early as possible in the design flow. The earlier they can budget mitigation solutions, the faster they will launch their product and the cheaper it will be to make those products reliable,” said Olivier Lauzeral, general manager, IROC Technologies Corp. “Offering a solution for very large designs, easy to use by non-specialists in SER, with a comprehensive approach to soft error analysis, has resulted in very high customer interest.”
SOCFIT is available now, through direct licensing. Some specific modules of the tool can be purchased separately, once customer licensed the core of the tool. SER data base for a particular node, the technology input of SOCFIT can be developed internally, outsourced as a service to iRoC, or licensed from foundries for standard cells. Available soon will be the TSMC 40G and 28 HP SER databases of their own cells .The SER database will be used for every SoC developed with the same cell library. TFIT and SOCFIT can be purchased as a bundle.
For technical papers and publications by IROC on soft errors, please see http://www.iroctech.com/info_21.html
IROC Technologies significantly lowers the risk of radiation-induced failure for integrated circuits (ICs) in the field, throughout a product’s lifetime, by optimizing the design. The company provides chip designers with soft error analysis software, test services and expert advisors to improve IC reliability and quality. TFIT and SOCFIT are used by companies that need high performance and high reliability in application areas such as cloud infrastructure, Internet infrastructure, automotive, medical devices and the military/ aerospace industry. IROC’s U.S. headquarters are in Silicon Valley, California, and its European headquarters are in Grenoble, France.
IROC Technologies is a registered trademark and TFIT and SOCFIT are trademarks of IROC Technologies. All other trademarks are the property of their respective owners.