Leading-Edge Semiconductor Technology Featured at SEMICON West

Industry Experts Discuss Latest Developments in Lithography, <22nm Process Development

SAN JOSE, Calif. — March 29, 2012 — The latest developments in <22nm process development and lithography will be featured in keynote presentations and free on-floor TechXPOT sessions during SEMICON West, July 10-12.  Shekhar Borkar, director of Extreme-scale Technologies at Intel Labs, will provide the technology keynote at 9:00am on Tuesday, July 10, discussing Intel’s mid- and long-term IC development efforts in scaling, power reduction, and performance improvements.  Separate two-hour TechXPOT sessions will be held on the latest technical achievements, challenges and barriers in photolithography, and advanced materials and processes for <22nm production.

Mobile and cloud computing are among the key drivers of the semiconductor industry.  With conventional scaling approaching its physical limits, the challenge falls to advanced materials and processes — and transistor architectures — to continue the drive to faster/smaller/thinner devices.  The SEMICON West South Hall TechXPOT session at 10:30am on Tuesday, July 10 will examine trends and issues with fully-depleted devices (e.g., FDSOI, FinFETs, tri-gate, etc.) and  the use of III-V channel materials   The speakers will discuss the latest developments, continued challenges, and ongoing research efforts in advanced process technology:

  • Raj Jammy, VP, Materials and Emerging Technologies, SEMATECH
  • Carlos Mazuré, EVP  and CTO, Soitec
  • Kaizad Mistry, VP, director of Logic Technology Integration, Intel
  • Aaron Thean, director, Logic Program, imec

Lithography challenges represent the single biggest threat to the continuation of Moore’s law.  The latest achievements, technology roadmaps and development efforts will be discussed on Wednesday, July 11 at 10:30am in the South Hall TechXPOT session.  Industry experts will examine continued efforts to commercialize EUVL, including productivity improvements, EUV transmission and conversion efficiency, and input power progress.  Additionally, EUV mask and resist infrastructure readiness activities, extension of double-patterning and the role of complementary technologies, such as e-beam lithography, will be addressed by the following speakers:

  • Yan Borodovsky, senior Intel fellow, director, Advanced Lithography, Intel
  • Stefan Wurm, director,  Lithography, SEMATECH
  • Hans Meiling, director, Product Management EUV, ASML
  • Franklin Kalk, CTO, Toppan Photomasks
  • Serge Tedesco, IMAGINE (MAPPER), program manager, CEA-Leti
  • Donis Flagello, NRCA fellow, Nikon Research Corporation of America

This year, SEMICON West is integrating the International Technology Roadmap for Semiconductors (ITRS) sessions into the TechXPOT and Extreme Electronics platforms on Thursday, July 12.  The Test Vision 2020 Conference will be held in conjunction with SEMICON West, on July 11-12.  In addition, a special session on supply chain opportunities in 450mm wafers will be held on Thursday, July 12.  Other TechXPOT sessions, yet to be announced, will address new materials, advances in 3D-IC, MEMS, test, advanced packaging, LEDs, OLEDs, and productivity solutions for 200mm and 300mm fabs. 

Over 31,000 people attended last year’s SEMICON West to learn, evaluate, and specify the latest in micro- and nanoelectronics manufacturing and development solutions. 

Register now for your FREE Expo Only badge (a $150 onsite value). Free registration ends April 12.  For more information, including keynotes, programs, registration, and exhibiting, please visit www.semiconwest.org.

The SEMICON West 2012 preview webinar is April 4 at 10:00am PDT. Sign up now to hear the latest on the technical sessions at SEMICON West.  

Companies with innovative technologies and solutions for advanced microelectronics manufacturing are invited to exhibit at SEMICON West. Great opportunities are still available —   learn more about exhibiting at SEMICON West.

Review Article Be the first to review this article
Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Job Openings: Can EDA Predict the Future
More Editorial  
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Engr, Elec Des 2 for KLA-Tencor at Milpitas, CA
Verification Engineer for Ambarella at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
ASIC Design Engineer for Ambarella at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy