Rambus to Present 10 Papers at DesignCon 2012

SANTA CLARA, Calif. — (BUSINESS WIRE) — January 30, 2012 — Rambus Inc. (NASDAQ: RMBS)

Who:

   

Rambus Inc. (NASDAQ: RMBS)

 

Where:

DesignCon 2012
Santa Clara Convention Center
Santa Clara, CA
 

When:

January 30 – February 2, 2012

At DesignCon 2012, Rambus engineers and scientists will present 10 technical papers on topics such as signal integrity, high-speed memory design and semiconductor security.

Additionally, the company is exhibiting (Booth #301) innovations from its Terabyte Bandwidth Initiative, DDR3 Memory Interface, Ultra-Fast Power-On Technology and Cryptography Research. For additional details, visit www.rambus.com.

Rambus Presentations:

Monday, January 30, 2012

Title: Managing Timing Jitter in High-speed Interface Design
1:30 p.m. - 4:30 p.m. – Ballroom F
Dan Oh, Ralf Schmitt and Chuck Yuan, Rambus Inc.

This session will discuss how as I/O speed continues to increase, timing errors due to random noise and power supply noise become a major bottleneck in high-speed I/O designs.

Tuesday, January 31, 2012

Title: Power Supply Noise Induced Jitter in a 6.4Gbps/Link Memory Interface System
8:30 a.m. - 9:10 a.m. – Ballroom E
Hai Lan, Ravi Kollipara, Sam Chang, Ling Yang, Lei Luo, Kashinath Prabhu, John Eble and Ralf Schmitt, Rambus Inc.

Rambus will discuss and explore the modeling methodology and analysis of supply noise and its jitter impact in a single-ended signaling memory interface operating at 6.4Gbps/link.

Title: Analysis and Characterization of Supply Noise and Its Jitter Impact in a 12.8Gbps Single-ended Signaling Memory Interface
11:05 a.m. – 11:45 a.m. – Ballroom F
Hai Lan, Minghui Han, Wendem Beyene, Chris Madden, Chuck Yuan and Ralf Schmitt, Rambus Inc.

This talk focuses on the analysis of supply noise induced jitter in 12.8Gbps advanced single-ended parallel interfaces with modeling results in correlation with on-chip measurement data.

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