Altera Experts Discuss Transceiver Technology, Floating Point DSP and Signal Integrity at DesignCon 2012

SAN JOSE, Calif., Jan. 25, 2012 — (PRNewswire) — Altera Corporation (NASDAQ: ALTR) today announced its participation at DesignCon 2012. Experts from Altera will showcase how they are solving some of the industry's most complex design challenges through 28-nm FPGA architectural innovations and advanced technologies that enable high-speed I/O performance, floating point DSP and best-in-class signal integrity. Altera's participation at DesignCon includes participation on industry panels, delivering a TechForum tutorial and presenting nine conference papers. For more information about Altera's participation at DesignCon visit http://www.altera.com/designcon.  

When:             

January 30 to February 2, 2012

Where:          

Santa Clara Convention Center

 

Santa Clara, Calif.

Panel Discussions: 

Monday, January 30
4:45 p.m.6:00 p.m., Ballroom E/F

Modern communication systems employ complex receivers that open the "closed EYE". Closed Eyes are difficult to specify so standards bodies have incorporated reference equalizers to measure the receiver stress in terms of an open EYE. Altera's Mike Li will join this panel to explore why differences must exist between the reference EQ and efficient silicon implementation.

Tuesday, January 31
3:45 – 5:00 p.m., Ballroom G

Altera's Daniel Chow will participate on this panel, which will feature engineers who characterize components that run at today's highest speeds. Panelists will share their experiences at making measurements and how they combine instruments to gain as much information as possible about a signal or system.

TechForum Tutorial Session:

Monday, January 30
9:00 a.m.12:00p.m., Ballroom F

This TechForum tutorial will review the latest design and verification developments, as well as architecture, circuit, and deep submicron process (40 nm, 28 nm) technology advancements for high-speed links, with an emphasis on jitter and signal integrity for up to 10- to 32-Gbps high-speed I/Os (e.g., GbE (10G, 100G), CEI/OIF (11G, 25-28G), OTN/OTU5 (32 G), Fibre Channel (16G, 32G), and PCI Express (8G, 16G)).

Paper Sessions:

Tuesday, January 31
8:30 a.m.9:10 a.m., Great America K

Tuesday, January 31
10:15 a.m.10:55 a.m., Ballroom F

Tuesday, January 31
11:05 a.m.11:45 a.m., Ballroom E

Tuesday, January 31
2:50 p.m.3:30 p.m., Great America 2

Wednesday, February 1
10:15 A.M. - 10:55 A.M., Great America 1

Wednesday, February 1
10:15 a.m.10:55 a.m., Great America 2

Wednesday, February 1
11:05 a.m.11:45 a.m., Ballroom E

Thursday, February 2
9:00 a.m.9:40 a.m., Ballroom G

Thursday, February 2
9:50 a.m.10:30 a.m., Ballroom H

About DesignCon
DesignCon is the largest meeting of board designers, and the only event to address chip design engineers' chip/system/package challenges. DesignCon features over 100 tutorials and technical paper sessions in 14 conference tracks focused on the pervasive nature of signal integrity at all levels of electronic design: chip, package, board, and system. For more information about DesignCon visit www.designcon.com.

About Altera
Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. Follow Altera via Facebook, RSS and Twitter.

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at  www.altera.com/legal.

Editor Contact:
Steve Gabriel
Altera Corporation
(408) 544-6846
Email Contact

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