SystemC Community Newsletter: Nov. 2011 -ESCUG, NASCUG Call for Papers; New TLM Videos

IN THIS ISSUE:

 

OSCI and Accellera to Unite

OSCI and Accellera, the leading industry organizations focused on the creation and adoption of EDA and IP standards plan to form a single organization. The new organization will leverage the complementary efforts of both groups to create more comprehensive standards to benefit the worldwide electronic design community, and facilitate efficient collaboration among its members. By joining forces, the combined organization will be able to accelerate development of system level standards that will move electronic design productivity to the next level. Said OSCI chair Eric Lish, "We are excited about the opportunity this presents to our members to improve their design productivity with industry standards that encompass system-level, RTL and gate-level design flows."

Watch for email regarding website access to the systemc.org and accellera.org websites.

Read the press release.

 

IEEE Approves Revised IEEE 1666™ Standard

The IEEE Standards Association (IEEE-SA) Standards Board has approved a revised version of the IEEE 1666™ "Standard SystemC Language Reference Manual,” which specifies SystemC, the high-level design language used in the design and development of electronic systems. The new version of IEEE 1666 encompasses many enhancements, notably the support for transaction-level modeling (TLM), a critical approach to enable higher level and more efficient design of complex integrated circuits (ICs) and system-on-chips (SoCs). "Systems designers and architects are faced with complex challenges that are a hybrid between hardware and software," said Judith Gorman, managing director, IEEE-SA. “The sheer complexity of today's SoCs and the demand for IP reuse make the need for standardized interoperability, collaboration and exchange of information a necessity to promote innovation. With the addition of TLM to IEEE 1666, the standard now addresses the specific needs of those system and hardware designers, who increasingly must find more effective ways of designing chips at smaller and smaller technology nodes."

Read the press release.

 

Call for Contributions for NASCUG Meeting at DVCon 2012

DVCon 2012North American SystemC Users Group Meeting
February 27, 2012
Co-located with DVCon 2012
San Jose, CA USA
www.nascug.org

The North American SystemC User’s Group (NASCUG) accelerates the use of SystemC for both new and established users by providing venues for users to contribute, learn, and interact. Following the great success of our previous meetings, we are calling for contributions to NASCUG 17 to be held Monday, February 27, 2012. The meeting is co-located with Design & Verification Conference 2012 (DVCon) in San Jose, California, USA.

A central component of the half-day user's group meeting is a number of short user experience presentations discussing techniques of design, modeling and verification using SystemC.

Abstract Deadline: Monday, 5 December 2011

See complete submission guidelines and online submission form >

 

Call for Contributions for ESCUG Workshop at DATE 2012
"OSCI and Accellera Core Technologies for the Next Generation of System-Level Design"

DATE ConferenceEuropean SystemC Users Group Workshop
Friday, March 16, 2012
8:30h - 16:30h
Co-located with DATE 2012
Workshop page: http://www.date-conference.com/conference/workshop-w6

The merger of the Open SystemC Initiative (OSCI) and Accellera unifies trendsetting standardization activities in the Electronic Design Automation (EDA) world and opens a wide range of new perspectives and synergies. The standards that are established and promoted by OSCI and Accellera cover a broad spectrum of today’s and tomorrow’s Electronic System Level (ESL) modeling and verification strategies.

This workshop is focused on the core technologies from both the OSCI and the Accellera world, and gives an outlook on how techniques may collaborate and converge. The format of the workshop includes four invited sessions from Doulos, Synopsys, Cadence, and ARM--providing a substantiated overview of the core technologies and their future way--and tutorial sessions--providing a practical guide on how those technologies can be successfully applied for improving a company's design strategy. In a second section, the workshop provides a platform for users to present their work based on OSCI and Accellera technologies.

Topic areas for the user section:

  • System-level modeling techniques (e.g., SystemC TLM)
  • System-level verification methodologies & integration of verification methodologies
  • IP handling and integration

If you are interested in presenting your work in our user section, please send an abstract (one page in PDF format) describing your work by December 2nd, 2011 to Email Contact. If you need any further information, please feel free to contact Email Contact.

  • Submission deadline: Friday, December 2nd, 2011
  • Notifcation of acceptance: Friday, December 9th, 2011

Also watch for the call for contributions for the ESCUG Users Group meeting to be held March 13.

 

New Technical Video Tutorial Now Online
"Software-Driven Verification Using TLM-2.0 Virtual Platforms"

Software-Driven Verification Using TLM-2.0 Virtual PlatformsIn addition to embedded software development, virtual platforms can effectively be deployed for software-driven verification, in which SystemC TLM-2.0 loosely-timed transaction-level platforms are connected by using transactors to signal-level representations of new subsystem hardware at the RT-level.

This tutorial provides both a detailed technology overview of software-driven verification techniques using loosely-timed SystemC TLM-2.0 based virtual platforms, and real-world case studies describing how these techniques benefit design teams.

The tutorial is split into five parts:

  • How We Got Here
    David Black, XtremeEDA Corporation

  • Software-Driven Verification Using TLM-2.0 Virtual Platforms
    John Aynsley, Doulos
  • LSI Axxia™ VDP Verification Using SystemC TLM-2.0
    Bill Bunton, LSI Corporation
  • Software-Driven Test Environment for TLM-IP Verification
    Volkan Esen, Infineon Technologies
  • TLM-2.0 Hybrid Virtual Platforms
    Trevor Wieman, Intel Corporation

Find out more and view the video tutorial.

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