HVD Technology to be formally announced and demonstrated at EDS Fair in Japan
TOKYO — (BUSINESS WIRE) — November 15, 2011 — Aldec, Inc. announces significant enhancements in its Riviera-PRO™ simulator and HES-DVM emulation platform that together create a complete SCE-MI (Standard Co-Emulation Modeling Interface) based co-emulation debugging environment - ensuring 100% visibility. Key areas of enhancement include HVD (Hardware Visibility-based Debugging) Technology for intelligent data extraction from the FPGA based emulator and the ability to transfer extracted data directly into the Riviera-PRO simulation database during emulation.
“Until now, hardware designers were forced to use multiple applications in addition to their simulator and emulator to ensure proper hardware signal data extraction and visualization,” said Zibi Zalewski, Hardware Products Division General Manager. “With this new release, Aldec provides a fully integrated debugging solution with improved functionality and simplified debugging flow.”
Built into the emulation solution, Aldec’s HVD technology analyzes RTL code to identify the minimal set of debugging probes that must be present in the emulation hardware to guarantee 100% visibility. This approach delivers up to 70% bandwidth savings in the critical emulator communication channel. Both dynamic and static probes from emulation can be visualized in the Riviera-PRO waveform viewer, preserving the original signal names and hierarchy paths and complete traceability to the design's RTL source code.
“The ability to use the same speed and debugging optimized simulation database for RTL simulation and emulation should simplify the design flow significantly,” added Dmitry Melnik, Riviera-PRO Product Manager. “Designers will be able to use the familiar debugging features of Riviera-PRO during emulation and eliminate the unnecessary steps of database conversion.”
Hardware Visibility-based Debugging (HVD) Technology is immediately available with Aldec’s integrated suite of products. To view HVD Technology resources, including an interactive movie, please visit http://www.aldec.com/Technologies/HVD.
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. More information about the company and its products is available at www.aldec.com.
Aldec and Riviera-PRO and are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Christina Toole, +(702) 990-4400