Accellera Chair Shishpal Rawat Talks About Roadmap for IP and System Design Standards at IP-SOC 2011

GRENOBLE, FRANCE -- (MARKET WIRE) -- Nov 03, 2011 --


Who
Accellera
, the electronics industry organization focused on electronic design automation (EDA) standards, invites IP-SOC 2011 attendees to hear Accellera chair Shishpal Rawat's invited talk on The Roadmap for IP and System Design Standards.

What
The Roadmap for IP and System Design Standards
Shishpal Rawat, Accellera Chair
System, software and semiconductor design activities are converging to meet the increasing challenges of creating SoCs. Accellera is working with OSCI and the SystemC working groups, as well as the IEEE and other standard bodies, to facilitate the creation of system design and IP standards that reduce the cost of electronic design and increase productivity. This presentation will cover our groups' standard activities -- IP Tagging, IP-XACT™, Open Verification Library (OVL), Standard Co-Emulation Modeling Interface (SCE-MI), Unified Coverage Interoperability Standard (UCIS) and Universal Verification Methodology (UVM™) -- the benefits of our standards, their fit with SystemC, and the roadmap for adoption.

When/Where
17:15 - 18:45, Wednesday, 7 December, 2011
World Trade Center
5 place Robert Schuman
38 000 Grenoble
France

Information and Registration
To register for IP-SOC, please visit http://www.design-reuse.com/ipsoc2011/registration/.
For more information about Accellera, please visit www.accellera.org.

About IP-SOC
IP-SOC is the leading industry event for the Intellectual Property (IP) and Embedded Electronic Systems community.

About Accellera
Accellera
provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA and IP standards that lower the cost to design commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are transferred to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.
For membership information, please email Email Contact.

UVM and IP-XACT are trademarks of Accellera Organization, Inc.
All other trademarks and tradenames are the property of their respective owners.

Add to Digg Bookmark with del.icio.us Add to Newsvine

Press Contact: 
Georgia Marszalek
ValleyPR LLC
+1 650-345-7477

Email Contact 





Review Article Be the first to review this article
Featured Video
Editorial
More Editorial  
Upcoming Events
MPSoc Forum 2017 - July 2 - 7, 2017, Les Tresoms Hotel, Annecy, France at Les Tresoms Hotel Annecy France - Jul 2 - 7, 2017
SEMICON West 2017 at Moscone Center San Francisco CA - Jul 11 - 13, 2017
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
DVCon India 2017, Sept 14 - 15, 2017 at The Leela Palace Bengalore India - Sep 14 - 15, 2017
NEC: CyberWorkbench
Verific: SystemVerilog & VHDL Parsers



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy